Displaying 3 results from an estimated 3 matches for "fp_lo".
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2006 Oct 02
2
[LLVMdev] returning a double in two registers
I have started to add support for FP in the ARM backend.
According to the ABI, 32 bit floating point numbers should be returned
in R0 and 64bit ones in R0/R1.
I have solved the 32 bit case by inserting bit_converts in LowerRET.
For the 64bit case I considered two options:
1) Creating two nodes. fp_lo and fp_hi. I could then select fmrdh and fmrdl with
(set IntRegs:$dst (bitconvert (fp_hi DFPRegs:$src))) and
(set IntRegs:$dst (bitconvert (fp_lo DFPRegs:$src)))
2) Create a node similar to copytoreg that has two results. This has
the advantage that it is possible to select fmrrd.
I am currently...
2006 Oct 02
0
[LLVMdev] returning a double in two registers
...backend.
cool.
> According to the ABI, 32 bit floating point numbers should be returned
> in R0 and 64bit ones in R0/R1.
Ok.
> I have solved the 32 bit case by inserting bit_converts in LowerRET.
Yep.
> For the 64bit case I considered two options:
>
> 1) Creating two nodes. fp_lo and fp_hi. I could then select fmrdh and fmrdl with
> (set IntRegs:$dst (bitconvert (fp_hi DFPRegs:$src))) and
> (set IntRegs:$dst (bitconvert (fp_lo DFPRegs:$src)))
Alternatively, you could merge bitconvert into the fp_hi/lo flags. That
would make the pattern simpler, and eliminate the ne...
2006 Oct 03
1
[LLVMdev] returning a double in two registers
> Alternatively, you could merge bitconvert into the fp_hi/lo flags. That
> would make the pattern simpler, and eliminate the need to have to match a
> bare fp_hi/fp_lo node without the bitconvert.
good point!
> Unfortunately, you can't do this elegantly in tblgen. You'd want to
> create an arm-local node at lowering time, then use custom C++ code to
> match it. The X86 backend has some examples of how to write the custom
> matching code, bu...