search for: fp16_to_fp

Displaying 8 results from an estimated 8 matches for "fp16_to_fp".

2017 Dec 04
2
[RFC] Half-Precision Support in the Arm Backends
...rpret the higher 16 bits in 32-bit registers and that would be wrong. Instead of trying to undo this early legalization/combining, I found this approach easier and cleaner. - As a consequence, the isel dags are in a more 'normal form'. I.e. it relies less on funny nodes FP_TO_FP16 and FP16_TO_FP, which are funny because they perform float up/down converts and produce i32 values by moving from/to integer and float registers. Instead, FP_EXTEND and FP_ROUND nodes will be introduced, so this is more a clean up rather than e.g. addressing a correctness issue. Unfortunatly I found that...
2017 Dec 06
2
[RFC] Half-Precision Support in the Arm Backends
Thanks a lot for the suggestions! I will look into using vld1/vst1, sounds good. I am custom lowering the bitcasts, that's now the only place where FP_TO_FP16 and FP16_TO_FP nodes are created to avoid inefficient code generation. I will double check if I can't achieve the same without using these nodes (because I really would like to get completely rid of them). Cheers, Sjoerd. >On 12/4/2017 6:44 AM, Sjoerd Meijer via llvm-dev wrote: >> >> Cus...
2018 Jan 18
0
[RFC] Half-Precision Support in the Arm Backends
...ets triggered because the ISEL DAG has indeed this funny node f16_to_fp (which models this register move and the float-convert): t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %0 t16: i32,ch = load<LD2[%addr], zext from i16> t0, t2, undef:i32 t12: f32 = fp16_to_fp t16 <~~~~~~~~ FUNNY NODE HERE t7: i32 = bitcast t12 t9: ch,glue = CopyToReg t0, Register:i32 %r0, t7 t10: ch = ARMISD::RET_FLAG t9, Register:i32 %r0, t9:1 And yes, to make it even funnier, this node has an i32 operand, and that's because we do the half-float load with an integer...
2018 Jan 18
1
[RFC] Half-Precision Support in the Arm Backends
...ets triggered because the ISEL DAG has indeed this funny node f16_to_fp (which models this register move and the float-convert): t0: ch = EntryToken t2: i32,ch = CopyFromReg t0, Register:i32 %0 t16: i32,ch = load<LD2[%addr], zext from i16> t0, t2, undef:i32 t12: f32 = fp16_to_fp t16 <~~~~~~~~ FUNNY NODE HERE t7: i32 = bitcast t12 t9: ch,glue = CopyToReg t0, Register:i32 %r0, t7 t10: ch = ARMISD::RET_FLAG t9, Register:i32 %r0, t9:1 And yes, to make it even funnier, this node has an i32 operand, and that's because we do the half-float load with an integer...
2019 Dec 10
2
TypePromoteFloat loses intermediate rounding operations
.... Basically only the place where the 16-bit size is needed to make the operation possible. Basically what we have is a very similar implementation to promoting integers, but that doesn't work for FP because we lose out on intermediate rounding. It seems like what we should instead do is insert fp16_to_fp and fp_to_fp16 in the libcall and arithmetic op handling. And use i16 to connect the legalized pieces together. Similar to how we use integer types when softening operations. I'm not sure if there would still be rounding issues with this, but it seems closer to matching the IR. Unfortunately,...
2019 Dec 10
2
TypePromoteFloat loses intermediate rounding operations
...he 16-bit size is needed to make > the operation possible. Basically what we have is a very similar > implementation to promoting integers, but that doesn't work for FP because > we lose out on intermediate rounding. > > > > It seems like what we should instead do is insert fp16_to_fp and > fp_to_fp16 in the libcall and arithmetic op handling. And use i16 to > connect the legalized pieces together. Similar to how we use integer types > when softening operations. I'm not sure if there would still be rounding > issues with this, but it seems closer to matching the...
2014 Jul 25
3
[LLVMdev] FPU cannot be compatible with -soft-float code on mips by llc
Hi all, -soft-float can not be rightly use by llc. All float function operation will call soft float, but not hard. My mips device cannot support half float type, so I hack the llvm, and add soft half float and add -soft-float option. I add the function define for __gnu_f2h_ieee() and __gnu_h2f_ieee (), and it can call the soft half float. However, all the others function about
2017 Dec 04
2
[RFC] - Deduplication of debug information in linkers (LLD)
...; Making f16 legal and not having native load/stores instructions > available, > > (no FullFP16 support) means custom lowering loads/stores: > > 1) Since we don't have FP16 load/store instructions available, we create > > integer half-word loads. I unfortunately need the FP16_TO_FP node > here, > > because that "models" creating an integer value, which is what we need > > to create a "truncating i16" integer load instructions. Instead, of > > using > > FP16_TO_FP, I have tried BITCASTs, but this can lead to code > gen...