Displaying 5 results from an estimated 5 matches for "format_rr".
2012 Aug 16
2
[LLVMdev] TableGen related question for the Hexagon backend
...ing InstFormat3; //pred true
string InstFormat4; //pred false
}
Define Instruction formats which are IFormat objects and have a unique
integer value
associated with them. It is used to access appropriate field within
RelHexagon Class.
def Format_prev : IFormat<0>; // previous form
def Format_rr : IFormat<1>; // register register
def Format_ri : IFormat<2>; // register immediate
def Format_predt : IFormat<3>; // pred true def Format_predf : IFormat<4>;
// pred false
4) Prototype relationship model for a simple 'add' instruction with 6
varia...
2012 Aug 02
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 1, 2012, at 1:53 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
>
> Currently, we rely on switch tables to transform between formats. However,
> we would like to have a different mechanism to represent these relationships
> instead of switch tables. I am thinking of modeling these relations in
> HexagonInstrInfo.td file and use TableGen to generate a table with
2012 Aug 01
3
[LLVMdev] TableGen related question for the Hexagon backend
Hi,
I'm looking for some suggestions on a problem related to the Hexagon
backend.
Hexagon architecture allows instructions in various formats. For example, we
have 3 variations of the add instruction as defined below:
ADDrr : r1 = add(r2, r3) --> add 2 32-bit registers ADDrr_p : if(p0) r1 =
add(r2, r3) --> predicated version of ADDrr instruction, executed when p0 is
true ADDrr_np :
2012 Aug 17
0
[LLVMdev] TableGen related question for the Hexagon backend
On Aug 16, 2012, at 1:39 PM, Jyotsna Verma <jverma at codeaurora.org> wrote:
> Hi Everyone,
>
> After some more thoughts to the Jacob's suggestion of using multiclasses for
> Opcode mapping, this is what I have come up with. Please take a look at the
> design below and let me know if you have any suggestions/questions.
Hi Jyotsna,
You are on to something here, but you
2012 Aug 17
2
[LLVMdev] TableGen related question for the Hexagon backend
...column
> identifier, there can be many different types of relationships between
> instructions.
We do have different type of relationships between instructions. I define
multiple IFormat objects one per relationship which finally translates into
a unique column into the mapping table.
def Format_rr : IFormat<1>;
def Format_ri : IFormat<2>;
def Format_predt : IFormat<3>;
def Format_predf : IFormat<4>;
Addrr : { Addrr, Addri, Addrr_pt, Addrr_pf, .. , ..}
Addri : { Addrr, Addri, Addri_pt, Addri_pf,..
> Do something like this:
>
> def getPredicatedOpcode : Inst...