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2012 Aug 06
2
[LLVMdev] ARM eabi calling convention
When I compile this program *$ cat vararg1-main.c typedef struct { double d; } S0; S0 g1; void foo0(int a, ...); int main(int argc, char **argv) { S0 s0 = { 2.0 }; foo0(1, s0); printf("%f\n", g1.d); * * return 0; }* with this command, *$ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7 -emit-llvm vararg1-main.c -S -o vararg1-main.ll -O3* I get this bitco...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
Yes, I see the load is 8-byte aligned in the bit code. My question was, assuming that arguments requiring double word alignment have to be passed in even/odd registers, how does the backend know that %0 has to be passed in register r2 and r3? *tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt * It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was originally a structure consisting of a single double field. When I run llc, it looks like "%0" is being passed in register r1 and r2. *$ llc vararg1-main.ll -o - ldr...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
On Aug 6, 2012, at 3:21 PM, Akira Hatanaka <ahatanak at gmail.com> wrote: > When I compile this program > > $ cat vararg1-main.c > > typedef struct { > double d; > } S0; > > S0 g1; > > void foo0(int a, ...); > > int main(int argc, char **argv) { > S0 s0 = { 2.0 }; > > foo0(1, s0); > > printf("%f\n", g1.d); > > return 0; > } > > with this command, > > $ clang -target arm-none-linux-gnueabi-gcc -ccc-clang-archs armv7 -emit-...
2012 Aug 07
0
[LLVMdev] ARM eabi calling convention
...load is 8-byte aligned in the bit code. > > My question was, assuming that arguments requiring double word alignment > have to be passed in even/odd registers, how does the backend know that %0 > has to be passed in register r2 and r3? > > tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt > > It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was > originally a structure consisting of a single double field. When I run llc, > it looks like "%0" is being passed in register r1 and r2. > > $ llc va...
2012 Oct 17
1
Do *not* pass '...' to NextMethod() - it'll do it for you; missing documentation, a bug or just me?
...ough I've done S3 dispatching for more than a decade now, I think I managed to overlook/avoid the following pitfall when using NextMethod(): If you explicitly pass argument '...' to NextMethod(), you will effectively pass those argument twice to the "next" method! EXAMPLE: foo0 <- function(...) UseMethod("foo0"); foo1 <- function(...) UseMethod("foo1"); foo2 <- function(...) UseMethod("foo2"); foo2.A <- foo1.A <- foo0.A <- function(object, a=1, b=2, c=3, d=4, ...) { str(c(list(object=object, a=a, b=b, c=c, d=d), list(...)...
2012 Nov 06
1
LazyData: no / yes
Hi the list I have package foo0 with a big dataset 'myData'. In DESCRIPTION, if I use 'LazyData: no', then I get: - when I open a R session : memory used=20 908 - when I attach 'library(foo0)' : memory used=24364 - then I load the set 'data(myData)' : memory used=39 668 If I use LazyData: y...
2012 Nov 06
1
Depends/Imports/Suggest/Enhence
Hi the list In the DESCRIPTION file of my package foo0, I have: Depends: foo1 Imports: foo2 Suggest: foo3 Enhence: foo4 If I understand correctly, to install foo0 on my computer, I need to already have foo1, foo2, foo3. foo4 is not necessary. I my R sesssion, when I will write: library(foo0), then the package foo1 will be attach. foo2, foo3 and fo...
2012 Aug 07
2
[LLVMdev] ARM eabi calling convention
...the bit code. >> >> My question was, assuming that arguments requiring double word alignment >> have to be passed in even/odd registers, how does the backend know that %0 >> has to be passed in register r2 and r3? >> >> tail call arm_aapcscc void (i32, ...)* @foo0(i32 1, [2 x i32] %0) nounwindt >> >> It doesn't seem that ARM backend can figure out that "[2 x i32] %0" was >> originally a structure consisting of a single double field. When I run llc, >> it looks like "%0" is being passed in register r1 and r2. &...
2012 Nov 07
2
Correct use of Depends, Imports and ::
Dear R developers, Taking advantage of the yesterday discussion about the use of Depends/Import/Suggests/Enhances, I would like to add a related question. Let's assume, in the DESCRIPTION file of my package foo0, I have: Depends: foo1 Imports: foo2 while in the NAMESPACE file of my package I have importFrom("foo2", f2) and within my package I use the following two external functions: f1, from package foo1 f2, from package foo2 If I want to use the two previous functions within a function...
2014 Dec 19
2
[LLVMdev] questions about ARM EABI attributes
...bute 20, 1 @ Tag_ABI_FP_denormal .eabi_attribute 21, 1 @ Tag_ABI_FP_exceptions .eabi_attribute 23, 3 @ Tag_ABI_FP_number_model Suppose there are two functions in a module which have different sets of function attributes. One function has attributes for "-ffast-math" (foo1) and the other (foo0) has attributes for "-fno-fast-math". In that case, which set of eabi attributes should ARMAsmPrinter::emitAttributes emit? ARMAsmPrinter::emitAttributes is called once at the start of a file (not once per every function), so I assume it has to merge those attributes which have different...
2004 Jun 14
5
mkChar can be interrupted
...ussed earlier in another thread and as documented in R-exts .Call() should not be interruptible by Ctrl-C. However the following code, which spends most of its time inside mkChar, turned out to be interruptible on RH-7.3 R-1.8.1 gcc-2.96: #include <Rinternals.h> #include <R.h> SEXP foo0(const SEXP nSexp) { int i, n; SEXP resSexp; if (!isInteger(nSexp)) error("wrong arg type\n"); n = asInteger(nSexp); resSexp = PROTECT(allocVector(STRSXP, n)); Rprintf("!!!time to interrup!!!\n"); for (i=0; i<n; ++i) { SET_STRING_ELT(resSexp, i, mk...
2015 Jun 02
2
[LLVMdev] [lld] TBSS wrong size
...nd found that it is generating wrong tbss size for case where multiple modules have non initialized threads variables. For instance: -- t0.c -- __thread int x0; __thread int x1; __thread int x2; extern __thread int e0; extern __thread int e1; extern __thread int e2; extern __thread int e3; int foo0 () { return x0; } int main () { return x0; } -- t1.c -- __thread int e0; __thread int e1; __thread int e2; __thread int e3; --- lld is generating (for aarch64): [14] .tbss NOBITS 0000000000401000 00001000 0000000000000010 0000000000000000 WAT 0 0...
2015 Apr 10
3
LXC and syslog seperation (/dev/log)
Hello, I'm seeing syslog messages "bleed" from the host and other LXC into the messages, maillog, secure logs of other LXCs. I'm using libvirt 1.0.0 on a host with systemd and kernel 3.9.10. Each LXC is running an older non-systemd linux distribution Is this a known issue? Is there a work around? Thank you for you time, Jim -- James R. Leu | Director of Technology | INOC
2008 Jan 18
1
validation - writeback in forms
...("user", "name", options_for_select(someArray))%> <%=select_tag ("formdata", "language1", options_for_select(someArray))%> <%=radio_button ("formdata", "language1_level, 3%> <% end> the controller has 2 functions, foo0 (displays the formular) and foo1 (validates data in params[:user]) if there is something wrong it renders the foo0 again, but only displays the entered contend of params[:user]. HOW do i get to display the enterd data for params[:formdata]. All formdata is not part of the model user, so i can'...
2015 Jun 03
3
[LLVMdev] [lld] TBSS wrong size
...bles. For instance: >> >> -- t0.c -- >> >> __thread int x0; >> __thread int x1; >> __thread int x2; >> >> extern __thread int e0; >> extern __thread int e1; >> extern __thread int e2; >> extern __thread int e3; >> >> int foo0 () >> { >> return x0; >> } >> >> int main () >> { >> return x0; >> } >> >> -- t1.c -- >> >> __thread int e0; >> __thread int e1; >> __thread int e2; >> __thread int e3; >> >> --- >> >&gt...
2010 Jan 19
4
Dom0 cache-ing MAC addresses?
I created a DomU with a dedicated network connection script path=''/usr/lib/xen/scripts/vif-dedicated'' Having run the virtual machine I now destroy the domain, undefine it, change the script to script path=''/usr/lib/xen/scripts/vif-vnic'' define the domain and try to start it. This fails. If I change the assigned MAC address the newly defined virtual
2017 Aug 01
7
[RFC] Add IR level interprocedural outliner for code size.
> > > > Also as a side note, I think in the original MachineOutliner RFC thread > there was some confusion as to whether it was possible to solve the code > folding outlining problem exactly as a graph problem on SSA using standard > value numbering algorithms in polynomial time. > > I can elaborate further, but > 1. it is easy to see that you can map an arbitrary
2014 Oct 12
2
[LLVMdev] Debug Info and MergeFunctions Transform
Hi David, After merging we always remove body of "G" (function we want to merge with "existing" one). In case with "writeThunk" we could add such info for "G", but it would be just a single string: reference to first string of "G". Ideal way here, is to merge debug information itself, and provide "F" with information for "G"
2005 Apr 27
23
eth0 & eth1 changing every boot
This is probably a stupid question, but I''m stumped. Practically every time my firewall boots (not often, but still) eth0 and eth1 exchange places (internet and intranet). How do I lock them down? SuSE 9.2, Shorewall 2.2.3. Thanks! Mike- -- Mornings: Evolution in action. Only the grumpy will survive. -- Please note - Due to the intense volume of spam, we have installed site-wide
2011 Dec 17
12
xl and vifname
...d to a bridge instead of the interface pairs. The tap devices /can/ be added to multiple bridges, so that''s a good start. Example of a use case: * dom0 has bridge br0, br1, br2, br3. * the (HVM) configuration contains this vif configuration: vif = [ ''script=vif-bridge, vifname=foo0, mac=00:16:3e:00:00:00, bridge=br0, model=e1000, type=ioemu'', ''script=vif-bridge, vifname=foo1, mac=00:16:3e:00:00:01, bridge=br1, model=e1000, type=ioemu'', ''script=vif-bridge, vifname=foo2, mac=00:16:3e:00:00:02, bridge=br2, model=e1000, type=ioe...