search for: foldimmedi

...s) MayLoad/MayStore and MoveImm seemed attractive/clean/efficient(?), if the instruction description did indeed use the flags. Hence the question. Thanks, Bharadwaj On Fri, Feb 9, 2018 at 12:17 PM, Craig Topper <craig.topper at gmail.com> wrote: > That flag is specifically used by the foldImmediate optimization in the > Peephole pass. We don't implement the TLI foldImmediate hook the peephole > pass uses on x86 so we have no reason to set the flag on any instructions > > What are you trying to do? > > ~Craig > > On Fri, Feb 9, 2018 at 11:45 AM, S. Bharadwaj Yada...

That flag is specifically used by the foldImmediate optimization in the Peephole pass. We don't implement the TLI foldImmediate hook the peephole pass uses on x86 so we have no reason to set the flag on any instructions What are you trying to do? ~Craig On Fri, Feb 9, 2018 at 11:45 AM, S. Bharadwaj Yadavalli via llvm-dev < llvm-dev at l...

Hi, I had (naively?) expected that the instruction to move immediate to register or memory (such as MOV32mi, MOV32ri, MOV64mi32, MOV64ri, MOV64ri32) would be marked with the flag MCID::MovImm via the X86InstrInfo.td (and hence in the generated X86GenInstrInfo.inc). I do not see that to be the case. Can someone please tell me if my expectation is flawed? Is there a better/different way to

...n/efficient(?), > if the instruction description did indeed use the flags. > > Hence the question. > > Thanks, > > Bharadwaj > > On Fri, Feb 9, 2018 at 12:17 PM, Craig Topper <craig.topper at gmail.com> > wrote: > >> That flag is specifically used by the foldImmediate optimization in the >> Peephole pass. We don't implement the TLI foldImmediate hook the peephole >> pass uses on x86 so we have no reason to set the flag on any instructions >> >> What are you trying to do? >> >> ~Craig >> >> On Fri, Feb 9, 201...

...of manual little transforms to clean things up. I know of the RFC for a new Combiner with its own syntax (https://reviews.llvm.org/D54286 is the latest I can find of it), but after manually adding my Nth manually coded pass for a niggling important transform, and then needing to add more cases to FoldImmediate/MemoryOperand/OptimizeLoad after it. I wondered how hard it would be to allow GlobalISel to reselect machine patterns, eg after they've been made available by other passes. What I was thinking is in addition to anything else that's coming, allowing Instructions to exist on the input sid...

Thanks! That looks like a winning approach. I swear I grepped around for ISD::Constant but for some reason never found this code. I think maybe I was searching for ISD::Constant with setOperationAction, which in hindsight was narrowing down my search to just lowering, which is exactly what I didn't want! (I was looking for other approaches). I also tried looking in depth at PowerPC but it

...C but it looks like it doesn't use this approach either. > > -- Sean Silva What’s the reason for trying to handle this in SelectionDAG at all? I would just materialize zero like any other constant, and treat replacing that with the zero register as an immediate folding optimization (e.g. FoldImmediate or another peephole pass) I thought about doing that, but I wasn't sure I could make it work. The issue is that the hardwired registers are actually the only way to write immediates of this register class (the registers are very small, obviously). I've been phrasing this as integer 0...

Hi Joe, Le 11/05/2012 02:13, Joe Matarazzo a écrit : > I've been unable to come up with the TableGen recipe to match a > negated operand. My target asm syntax allows the following transform: > > FNEG r8, r5 > MUL r6, r8, r9 > > to > > MUL r6, -r5, r9 > > Is there a Pattern<> syntax that would allow matching *any* opcode (or > even some

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops