search for: fnstsw

...1716043B mov eax,76E4560h 17160440 mov dword ptr [esp],eax 17160443 call HueVMReadCommands_LLVMReadVoxel (19BB229h) 17160448 fsub dword ptr ds:[161D6280h] 1716044E fabs 17160450 fst qword ptr [esp+14h] 17160454 ftst 17160456 fstp st(0) 17160458 fnstsw ax 1716045A sahf 1716045B fldz 1716045D fchs 1716045F fld qword ptr [esp+14h] 17160463 fucomip st,st(1) 17160465 fstp st(0) 17160467 jbe 17160498 1716046D mov eax,76E4F60h 17160472 mov dword ptr [esp+0Ch],eax 17160476 fld qword ptr [...

...ng _both_ the SAHF and the fucomi -- look at the code ISelPattern generates: 17160443 call HueVMReadCommands_LLVMReadVoxel (19BB229h) 17160448 fsub dword ptr ds:[161D6280h] 1716044E fabs 17160450 fst qword ptr [esp+14h] 17160454 ftst 17160456 fstp st(0) 17160458 fnstsw ax 1716045A sahf 1716045B fldz 1716045D fchs 1716045F fld qword ptr [esp+14h] 17160463 fucomip st,st(1) 17160465 fstp st(0) 17160467 jbe 17160498 the ISelSimple generates: 1716047F call eax 17160481 fsub dword ptr ds:[16237240h] 17160487 fab...

...into the map somehow?"), function AddLegalizedOperand, file /usr/home/llvm/obj/../lib/CodeGen/SelectionDAG/LegalizeDAG.cpp, line 79. .text .align 16 .globl test1 .type test1, @function test1: fldl 4(%esp) ftst fstp %st(0) fnstsw sahf setne %al movzbl %al, %eax #FP_REG_KILL ret Abort trap (core dumped) FAIL: /usr/home/llvm/obj/../test/Regression/CodeGen/X86/fast-cc-pass-in-regs.ll: Does not have a RUN line Running /usr/home/llvm/obj/../test/Regression/Debugger/dg.exp ... FAIL: /usr...

On Wed, 16 Mar 2005, Morten Ofstad wrote: > Hello, > > I didn't get any reply to my previous mail about adding floating point > intrinsics to the X86 pattern instruction selector... And I could really need > some help. Sorry about that, it slipped through the cracks. :( > Anyway, I think my confusion was caused partly by an already > existing bug in the instruction

Hello, I didn't get any reply to my previous mail about adding floating point intrinsics to the X86 pattern instruction selector... And I could really need some help. Anyway, I think my confusion was caused partly by an already existing bug in the instruction selection for floating point compares. The case which emits code for the special case of comparing against constant 0.0 does not

Hello, I am trying to make the FP intrinsics (abs, sin, cos, sqrt) I've added work with the X86ISelPattern, but I'm having some difficulties understanding what needs to be done. I assume I have to add new nodetypes for the FP instructions to SelectionDAGNodes.h, and make nodes for these in SelectionDAGLowering::visitCall when I find the intrinsic... The part I don't quite

...ware. It appears to work fine, and OS/2 is now finally working on Intel/VT as well as AMD/SVM. I''m a little concerned about the "correctness" of the FSTSW emulation and the use of inline assembly directly using the corresponding ops for emulation. Wrt FSTSW, it is really two ops FNSTSW immediately preceeded by an FWAIT. I''ve left FWAIT defined, but a no-op because after looking at realmode.c it seems in the emulation, exceptions are always processed if a call to x86_emulate returns an exception, so there should be no way for there to be "pending" exceptions for...

...ou as soon as I have put it up for review. As far as I'm aware, the bugfix should be relatively version-agnostic, so you should not have too much trouble backporting it. The solution basically works like this: * Model FPSW (the FPU status word) as a register. * Add ISel patterns for the FCOM*, FNSTSW and SAHF instructions. * During Legalize/Lowering, build a node sequence to transport the comparison result from FPSW into EFLAGS. The patch itself is already finished, but I want to add a few test cases before submitting it (probably during the weekend if I find the time). Cheers, Christoph Am...

Hello there, I recently started working on the LLVM backend for a target that doesn't support x87 instructions. Currently, I am in the process of completely disabling some x87 instructions such as fcomi, fcompi,... for a specific sub-target. I also do not have SSE enabled for my sub-target, and llvm resorts to fcomi* instructions for FP compare instructions. Is there a way to bypass the

...# float -0.5 .text .globl main .align 16, 0x90 .type main, at function main: # @main .cfi_startproc # BB#0: fldl g fmuls .LCPI0_0 fldz fchs fxch %st(1) fucompp fnstsw %ax # kill: AX<def> AX<kill> EAX<def> # kill: AH<def> AH<kill> EAX<kill> sahf sete %al movzbl %al, %eax retl .Ltmp0: .size main, .Ltmp...