Displaying 2 results from an estimated 2 matches for "fmul2rdrr".
2017 Feb 26
2
When AVR backend generates mulsu instruction ?
Hello LLVMDevs,
I am looking for an example for how to lower LLVM IR to mulsu kind of
instruction. I found that AVR back end have such instruction but
AVRInstrInfo.td does not define any DAG pattern for which this
instruction gets emitted.
def MULSURdRr : FMUL2RdRr<1,
(outs),
(ins GPR8:$lhs, GPR8:$rhs),
"mulsu\t$lhs, $rhs",
[]>,
Requires<[SupportsMultiplication]>;
Also simple grep around related words does not show any other information.
Can some one explain me how this kind of instruction should be lowered ?
Sincerely,
Vivek
--------...
2017 Feb 27
2
When AVR backend generates mulsu instruction ?
...evs,
>>
>> I am looking for an example for how to lower LLVM IR to mulsu kind of
>> instruction. I found that AVR back end have such instruction but
>> AVRInstrInfo.td does not define any DAG pattern for which this
>> instruction gets emitted.
>> def MULSURdRr : FMUL2RdRr<1,
>> (outs),
>> (ins GPR8:$lhs, GPR8:$rhs),
>> "mulsu\t$lhs, $rhs",
>> []>,
>> Requires<[SupportsMultiplication]>;
>> Also simple grep around related words does not show any other
>> information.
>>
>> Can some one explai...