Displaying 2 results from an estimated 2 matches for "fmrrd".
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flerd
2006 Oct 02
2
[LLVMdev] returning a double in two registers
...eating two nodes. fp_lo and fp_hi. I could then select fmrdh and fmrdl with
(set IntRegs:$dst (bitconvert (fp_hi DFPRegs:$src))) and
(set IntRegs:$dst (bitconvert (fp_lo DFPRegs:$src)))
2) Create a node similar to copytoreg that has two results. This has
the advantage that it is possible to select fmrrd.
I am currently trying to implement 2, but I am not sure how to declare
an instruction that has two results. There are some combined mod/rem
instruction like idivl, but they have fixed defs (EAX, EDX).
I have just committed a partial version that doesn't declare fmrrd as
defining its two inte...
2006 Oct 02
0
[LLVMdev] returning a double in two registers
...could merge bitconvert into the fp_hi/lo flags. That
would make the pattern simpler, and eliminate the need to have to match a
bare fp_hi/fp_lo node without the bitconvert.
> 2) Create a node similar to copytoreg that has two results. This has
> the advantage that it is possible to select fmrrd.
>
> I am currently trying to implement 2, but I am not sure how to declare
> an instruction that has two results. There are some combined mod/rem
> instruction like idivl, but they have fixed defs (EAX, EDX).
Unfortunately, you can't do this elegantly in tblgen. You'd want to...