search for: fmdrr

...l, I tried same code on gcc for arm(hard float), double f2 () { double x = 10.0; asm ("" : "=r" (x) : "0" (x)); return x; } > arm-linux-gnueabi-gcc -S -mhard-float pr39058.c -O2 Generates proper code, mov r3, #0 mov r2, #0 movt r3, 16420 fmdrr d0, r2, r3 bx lr But llvm crashes, If data type is "double", register type is "int". Any comments why does llvm currently handle this case ? Regards, Rajesh On Wed, Nov 21, 2012 at 3:19 PM, rajesh viswabramana < viswabramana.rajesh at gmail.com> wrote: >...

I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $resul...

Thanks Rafael, Hello All, Could anyone please comment, which part in selectiondag need to be understood/modified to fix this. Regards, Rajesh On Wed, Nov 21, 2012 at 2:38 AM, Rafael Espíndola < rafael.espindola at gmail.com> wrote: > I reported http://llvm.org/pr14393 to track it. > > On 20 November 2012 05:18, rajesh viswabramana > <viswabramana.rajesh at

...mdev at cs.uiuc.edu> 日期: 2009,220,周五,1:11上午 Currently there is no constraint that tells the register allocator to allocate a consecutive register pair. What I would suggest you do is to declare pseudo register pair registers (and corresponding register class, say PAIR_GPR). In this case, your myFMDRR would take one input of PAIR_GPR class. The asm printer should be taught to print a PAIR_GPR register as two GPR registers (you should also teach the JIT of the same thing). A PAIR_GPR register should be a super register of two GPR registers. e.g. r0r1_pair is a super register of r0 and r1. In ord...

...09,220,周五,1:11上午 > > Currently there is no constraint that tells the register allocator > to allocate a consecutive register pair. What I would suggest you do > is to declare pseudo register pair registers (and corresponding > register class, say PAIR_GPR). In this case, your myFMDRR would take > one input of PAIR_GPR class. The asm printer should be taught to > print a PAIR_GPR register as two GPR registers (you should also > teach the JIT of the same thing). > > A PAIR_GPR register should be a super register of two GPR registers. > e.g. r0r1_pair is...

...; { > double x = 10.0; > > asm ("" : "=r" (x) : "0" (x)); > return x; > } > >> arm-linux-gnueabi-gcc -S -mhard-float pr39058.c -O2 > > Generates proper code, > mov r3, #0 > mov r2, #0 > movt r3, 16420 > fmdrr d0, r2, r3 > bx lr > > But llvm crashes, If data type is "double", register type is "int". > Any comments why does llvm currently handle this case ? "r" is supposed to be a single register, not a register pair; the fact that gcc accepts this is p...

...mdev at cs.uiuc.edu> 日期: 2009,220,周五,1:11上午 Currently there is no constraint that tells the register allocator to allocate a consecutive register pair. What I would suggest you do is to declare pseudo register pair registers (and corresponding register class, say PAIR_GPR). In this case, your myFMDRR would take one input of PAIR_GPR class. The asm printer should be taught to print a PAIR_GPR register as two GPR registers (you should also teach the JIT of the same thing). A PAIR_GPR register should be a super register of two GPR registers. e.g. r0r1_pair is a super register of r0 and r1. In ord...

...mdev at cs.uiuc.edu> 日期: 2009,220,周五,1:11上午 Currently there is no constraint that tells the register allocator to allocate a consecutive register pair. What I would suggest you do is to declare pseudo register pair registers (and corresponding register class, say PAIR_GPR). In this case, your myFMDRR would take one input of PAIR_GPR class. The asm printer should be taught to print a PAIR_GPR register as two GPR registers (you should also teach the JIT of the same thing). A PAIR_GPR register should be a super register of two GPR registers. e.g. r0r1_pair is a super register of r0 and r1. In or...