search for: fma4

Hi, A question from r162999 changes: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFMA.td?r1=162999&r2=162998&pathrev=162999 For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and "MemOp4" like those of "rm" or "rr" ? multiclass fma4s< > ... def mr : FMA4<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2, RC:$src3), !strconcat(Opc...

Hi All, I am facing miscompare error when running povray (and few other C/C++ benchmarks) from spec cpu2006 suite enabling FMA4 (and disabling FMA3). I have used -ffp-contract=fast to turn on this option. (Compilation options and targets pasted below). >>>>>>>> clang version 3.2 (trunk 163295:163308) (llvm/trunk 163295) Target: x86_64-unknown-linux-gnu Thread model: posix (Options to clang) -O3...

On 8 November 2012 11:12, Cameron McInally <cameron.mcinally at nyu.edu> wrote: > On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com> > wrote: > ... >> >> For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and >> "MemOp4" like those of "rm" or "rr" ? > > > Hey Anitha, > > The VEX.W bit is used to denote operand order. In other words, this bit > allows for a memop to be used as eith...

On Wed, Nov 7, 2012 at 10:52 PM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > For the multiclass "fma4s", why is "mr" not inherited from "VEX_W" and > "MemOp4" like those of "rm" or "rr" ? > Hey Anitha, The VEX.W bit is used to denote operand order. In other words, this bit allows for a memop to be used as either the second or third sour...

On 10/04/2014 16:32, Tom Stellard wrote: > On Wed, Apr 09, 2014 at 06:47:19PM +0200, Sylvestre Ledru wrote: >> Hello, >> >> Trying the 3.4.1 branch, I get following tests failing: >> LLVM :: CodeGen/X86/2009-06-05-VZextByteShort.ll >> LLVM :: CodeGen/X86/fma4-intrinsics-x86_64.ll >> LLVM :: CodeGen/X86/fp-fast.ll >> LLVM :: CodeGen/X86/vec_shift4.ll >> LLVM :: CodeGen/X86/vshift-4.ll >> >> I am testing on a Debian testing 64b. >> Does it ring a bell? >> > Can anyone else reproduce this? These tes...

...a lion's share of such a change implemented already and performance is greatly affected. If the community is interested in this change, I would be happy to prepare a patch. -Cameron On Thu, Jul 26, 2012 at 2:27 PM, Jan Sjodin <jan_sjodin at yahoo.com> wrote: > You can't execute FMA4 instructions on Intel processors, so it doesn't > really matter what the impact of the move instructions would be, since it > would end up with an illegal instruction regardless. :) It does perhaps > bring up an issue of tuning for different architectures, but that is > something no...

We're migrating to LLVM 3.1 and trying to use the upstream FMA patterns. Why is VFMADDSD4 defined with vector types? Is this simply because the gcc intrinsic uses vector types? It's quite unnatural if you have a compiler that generates FMAs as opposed to requiring user intrinsics. -Dave

Because the intrinsics uses vector types (same as gcc). - Jan ----- Original Message ----- > From: "dag at cray.com" <dag at cray.com> > To: llvmdev at cs.uiuc.edu > Cc: > Sent: Wednesday, July 25, 2012 3:26 PM > Subject: [LLVMdev] X86 FMA4 > > We're migrating to LLVM 3.1 and trying to use the upstream FMA patterns. > > Why is VFMADDSD4 defined with vector types?  Is this simply because the > gcc intrinsic uses vector types?  It's quite unnatural if you have a > compiler that generates FMAs as opposed to re...

Hello, Trying the 3.4.1 branch, I get following tests failing: LLVM :: CodeGen/X86/2009-06-05-VZextByteShort.ll LLVM :: CodeGen/X86/fma4-intrinsics-x86_64.ll LLVM :: CodeGen/X86/fp-fast.ll LLVM :: CodeGen/X86/vec_shift4.ll LLVM :: CodeGen/X86/vshift-4.ll I am testing on a Debian testing 64b. Does it ring a bell? Sylvestre

...vector types (same as gcc). > > > - Jan > > > > ----- Original Message ----- > > From: "dag at cray.com" <dag at cray.com> > > To: llvmdev at cs.uiuc.edu > > Cc: > > Sent: Wednesday, July 25, 2012 3:26 PM > > Subject: [LLVMdev] X86 FMA4 > > > > We're migrating to LLVM 3.1 and trying to use the upstream FMA patterns. > > > > Why is VFMADDSD4 defined with vector types? Is this simply because the > > gcc intrinsic uses vector types? It's quite unnatural if you have a > > compiler that gen...

I have seen some re-factoring work done to prepare for AVX support. What are the plans (time wise) to add the AVX patterns to the backend? Has anyone thought about FMA4? - Jan

Jan Sjodin <jan_sjodin at yahoo.com> writes: > You can't execute FMA4 instructions on Intel processors, so it doesn't > really matter what the impact of the move instructions would be, since > it would end up with an illegal instruction regardless. :) Interlagos? All the world is not Intel. > It does perhaps bring up an issue of tuning for different...

...of such a change implemented already and performance is greatly affected. If the community is interested in this change, I would be happy to prepare a patch. > > -Cameron > > On Thu, Jul 26, 2012 at 2:27 PM, Jan Sjodin <jan_sjodin at yahoo.com> wrote: > You can't execute FMA4 instructions on Intel processors, so it doesn't really matter what the impact of the move instructions would be, since it would end up with an illegal instruction regardless. :) It does perhaps bring up an issue of tuning for different architectures, but that is something nobody is really looki...

On Wednesday 24 February 2010 18:47:19 Dan Gohman wrote: > SDUse's Prev and Next members implement a use list. Copying them > probably wouldn't immediately break anything, but it wouldn't be > meaningful. I understand that the copied SDUse wouldn't be represented in the list, so I can understand the general reasons for making the copy constructor private. In this case,

On Thursday 25 February 2010 15:33:58 Jan Sjodin wrote: > I have seen some re-factoring work done to prepare for AVX support. What > are the plans (time wise) to add the AVX patterns to the backend? Has > anyone thought about FMA4? Oh yes. :) FMA4 will have a different feature bit than AVX or FMA3. FMA4 is our top priority after AVX due to Bulldozer. What would you like to see for FMA4? I will be implementing that just as soon as I push up some more AVX support. The AVX work is ready to be pushed up and I am working...

On Fri, Jul 27, 2012 at 2:37 PM, Michael Gottesman <mgottesman at apple.com> wrote: ... > I have actually timed said instructions in the past and reproduced Agner > Fog's results. I just prefer to speak by referring to facts that can not be > misconstrued as hearsay = ). That would be great. Also, can you point me to the Agner Fog table that you are referring to? Thanks.

On Thu, Nov 8, 2012 at 1:34 AM, Anitha Boyapati <anitha.boyapati at gmail.com>wrote: ... > > I actually have confusion in mapping the role of vex_w during > instruction selection. For the moment, lets just consider vex_w and > not memop. > > [1]. What does " def rr : FMA4<>, VEX_W" mean? As per tablegen > description, "rr" now inherits FMA4 and VEX_W. However VEX_W is not a > class, it is an enumerated value. > > VEX_W is a class, which sets the VEX.W bit to 1. > class VEX_W { bit hasVEX_WPrefix = 1; } > [2]. How does vex...

...implemented already and performance > is greatly affected. If the community is interested in this change, I would > be happy to prepare a patch. > > -Cameron > > On Thu, Jul 26, 2012 at 2:27 PM, Jan Sjodin <jan_sjodin at yahoo.com> wrote: > >> You can't execute FMA4 instructions on Intel processors, so it doesn't >> really matter what the impact of the move instructions would be, since it >> would end up with an illegal instruction regardless. :) It does perhaps >> bring up an issue of tuning for different architectures, but that is >&...

...plemented already and performance is greatly affected. If the community is interested in this change, I would be happy to prepare a patch. >> >> -Cameron >> >> On Thu, Jul 26, 2012 at 2:27 PM, Jan Sjodin <jan_sjodin at yahoo.com> wrote: >> You can't execute FMA4 instructions on Intel processors, so it doesn't really matter what the impact of the move instructions would be, since it would end up with an illegal instruction regardless. :) It does perhaps bring up an issue of tuning for different architectures, but that is something nobody is really looki...

...oyapati at gmail.com> wrote: > On 11 March 2013 17:00, Duncan Sands <baldrick at free.fr> wrote: > > Hi Anitha, > > > > > >> Ah, I am taking back my above words w.r.t encoding. -no-integrated-as > >> does fix the issue! This definitely points towards FMA4 encoding in > >> clang's integrated assembler. This fits into the analysis as well - > >> dragonegg *might not* be using integrated assembler at all. > > > > > > you are right, dragonegg does not use the integrated assembler. > > Thanks for the confirma...