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2017 Apr 03
2
Scheduler: modelling long register reservations?
...ncorrectly? Can llvm support this kind of constraint?
Thank you,
Nick Johnson
D. E. Shaw Research
// Excerpted from lib/Target/MyTarget/MyTargetSchedule.td:
//
def DesGCv3GenericModel : SchedMachineModel
{
let IssueWidth = 1;
let MicroOpBufferSize = 0;
let CompleteModel = 1;
}
// ...
def FlexU : ProcResource<64> { let BufferSize = 1; }
def : WriteRes<IIFlexRead, [FlexU]> { let Latency = 25; let ResourceCycles = [25]; }
class SchedFlexRead : Sched< [IIFlexRead] >; // I apply this to the definition of FXLV instruction
// ...