Displaying 4 results from an estimated 4 matches for "fldi".
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2009 Mar 30
1
[LLVMdev] Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
..."mytarget", [f64], 64,[FD0, FD1, ....]
When I move f64 to even/odd pair register, I first move f64 into GPR64,
then move to 2 GPR32 register.
It worked very well for register binding.
But When I test some case. I find a register class error.
--------------
11405 0x9321bc8: f64,ch = FLDI 0x93436f8, 0x9343c20, 0x9321ac0, 0x9343674 --
|
|
11428 0x9321304: f64 = Register #1066---------| |
153 11429 0x9321bc8: <mul...
2009 Mar 31
1
[LLVMdev] 转发: Re: Dear Evan Chang, Re: help: about how to use tblgen to constraint operand.
...quot;mytarget", [f64], 64,[FD0, FD1, ....]
When I move f64 to even/odd pair register, I first move f64 into GPR64,
then move to 2 GPR32 register.
It worked very well for register binding.
But When I test some case. I find a register class error.
--------------
11405 0x9321bc8: f64,ch = FLDI 0x93436f8, 0x9343c20, 0x9321ac0, 0x9343674
--
|
|
11428 0x9321304: f64 = Register
#1066---------| |
153 11429 0x9321bc8: <m...
2009 Feb 20
0
[LLVMdev] help: about how to use tblgen to constraint operand.
On Feb 19, 2009, at 8:26 PM, 任坤 wrote:
> hi, Dear Evan Cheng:
>
> My cpu is i32 embeded CPU. I define pseudo register pair registers.
>
> In mytargetRegisterInfo.td:
> def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
> ...
> def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
>
> In mytargetISelLowering.cpp:
> I define i1, i8 ,
2009 Feb 20
2
[LLVMdev] help: about how to use tblgen to constraint operand.
hi, Dear Evan Cheng:
My cpu is i32 embeded CPU. I define pseudo register pair registers.
In mytargetRegisterInfo.td:
def T0: RegisterWithSubRegs<"t0",[R0,R1]>;
...
def GPR64 : RegisterClass<"mytarget", [i64], 64, [T0, T1.....]
In mytargetISelLowering.cpp:
I define i1, i8 , i16 and i32 are legal.
1. I still have problem. I save my function return double value in