search for: fixup_pointer

Displaying 20 results from an estimated 31 matches for "fixup_pointer".

2020 Jul 24
0
[PATCH v5 34/75] x86/head/64: Make fixup_pointer() static inline
...etup(void) { } extern struct boot_params boot_params; extern char _text[]; +/* + * This function is used in C code that runs while the kernel still runs on + * identity mapped addresses to get the correct address of kernel pointers in + * the identity mapping. + */ +static __always_inline void *fixup_pointer(void *ptr, unsigned long physaddr) +{ + return ptr - (void *)_text + (void *)physaddr; +} + static inline bool kaslr_enabled(void) { return IS_ENABLED(CONFIG_RANDOMIZE_MEMORY) && diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index b0ab5627900b..8703292a35e9 100644 ---...
2020 Aug 31
2
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
...initdata = { > + .size = IDT_TABLE_SIZE - 1, > + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */, > +}; > + > +void __init early_idt_setup(unsigned long physbase) > +{ > + void __maybe_unused *handler; > + gate_desc *idt; > + > + idt = fixup_pointer(idt_table, physbase); > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + /* VMM Communication Exception */ > + handler = fixup_pointer(vc_no_ghcb, physbase); > + set_early_idt_handler(idt, X86_TRAP_VC, handler); This function is used only once AFAICT - you might just as well add its three-lin...
2020 Aug 31
2
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
...initdata = { > + .size = IDT_TABLE_SIZE - 1, > + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */, > +}; > + > +void __init early_idt_setup(unsigned long physbase) > +{ > + void __maybe_unused *handler; > + gate_desc *idt; > + > + idt = fixup_pointer(idt_table, physbase); > + > +#ifdef CONFIG_AMD_MEM_ENCRYPT > + /* VMM Communication Exception */ > + handler = fixup_pointer(vc_no_ghcb, physbase); > + set_early_idt_handler(idt, X86_TRAP_VC, handler); This function is used only once AFAICT - you might just as well add its three-lin...
2020 Sep 07
0
[PATCH v7 39/72] x86/sev-es: Setup early #VC handler
...esc desc; + + init_idt_data(&data, n, handler); + idt_init_desc(&desc, &data); + native_write_idt_entry(bringup_idt_table, n, &desc); +} +#endif + /* This runs while still in the direct mapping */ static void startup_64_load_idt(unsigned long physbase) { struct desc_ptr *desc = fixup_pointer(&bringup_idt_descr, physbase); + void __maybe_unused *handler; + +#ifdef CONFIG_AMD_MEM_ENCRYPT + /* VMM Communication Exception */ + handler = fixup_pointer(vc_no_ghcb, physbase); + set_bringup_idt_handler(X86_TRAP_VC, handler); +#endif desc->address = (unsigned long)fixup_pointer(bring...
2020 Jul 24
0
[PATCH v5 30/75] x86/head/64: Setup MSR_GS_BASE before calling into C code
...lt;asm/realmode.h> /* * Manage page tables very early on. @@ -513,6 +514,8 @@ void __init x86_64_start_reservations(char *real_mode_data) */ void __head startup_64_setup_env(unsigned long physbase) { + unsigned long gsbase; + /* Load GDT */ startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); native_load_gdt(&startup_gdt_descr); @@ -521,4 +524,8 @@ void __head startup_64_setup_env(unsigned long physbase) asm volatile("movl %%eax, %%ds\n" "movl %%eax, %%ss\n" "movl %%eax, %%es\n" : : "a"(__KERNEL_DS)...
2020 Aug 24
0
[PATCH v6 31/76] x86/head/64: Setup MSR_GS_BASE before calling into C code
...lt;asm/realmode.h> /* * Manage page tables very early on. @@ -513,6 +514,8 @@ void __init x86_64_start_reservations(char *real_mode_data) */ void __head startup_64_setup_env(unsigned long physbase) { + unsigned long gsbase; + /* Load GDT */ startup_gdt_descr.address = (unsigned long)fixup_pointer(startup_gdt, physbase); native_load_gdt(&startup_gdt_descr); @@ -521,4 +524,8 @@ void __head startup_64_setup_env(unsigned long physbase) asm volatile("movl %%eax, %%ds\n" "movl %%eax, %%ss\n" "movl %%eax, %%es\n" : : "a"(__KERNEL_DS)...
2020 Aug 24
0
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
...endif + +static struct desc_ptr early_idt_descr __initdata = { + .size = IDT_TABLE_SIZE - 1, + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */, +}; + +void __init early_idt_setup(unsigned long physbase) +{ + void __maybe_unused *handler; + gate_desc *idt; + + idt = fixup_pointer(idt_table, physbase); + +#ifdef CONFIG_AMD_MEM_ENCRYPT + /* VMM Communication Exception */ + handler = fixup_pointer(vc_no_ghcb, physbase); + set_early_idt_handler(idt, X86_TRAP_VC, handler); +#endif + + /* Initialize IDT descriptor and load IDT */ + early_idt_descr.address = (unsigned long)idt; +...
2020 Sep 01
0
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
On Mon, Aug 31, 2020 at 11:45:41AM +0200, Borislav Petkov wrote: > On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote: > > +#ifdef CONFIG_AMD_MEM_ENCRYPT > > + /* VMM Communication Exception */ > > + handler = fixup_pointer(vc_no_ghcb, physbase); > > + set_early_idt_handler(idt, X86_TRAP_VC, handler); > > This function is used only once AFAICT - you might just as well add its > three-lined body here and save yourself the function definition and > ifdeffery above... True, but having a separate funct...
2020 Apr 28
0
[PATCH v3 70/75] x86/head/64: Setup TSS early for secondary CPUs
...(&tss_desc, (unsigned long)tss, DESC_TSS, + __KERNEL_TSS_LIMIT); + native_write_gdt_entry(gdt, GDT_ENTRY_TSS, &tss_desc, DESC_TSS); + + asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8)); +} + void __head early_idt_setup(unsigned long physbase) { gate_desc *idt = fixup_pointer(idt_table, physbase); diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 4d84a0c72e36..7f2d5e14db73 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -220,6 +220,9 @@ SYM_CODE_START(secondary_startup_64) */ movq initial_stack(%rip), %rsp + /* Set...
2020 Aug 24
0
[PATCH v6 36/76] x86/head/64: Load IDT earlier
...{ unsigned int vector; @@ -385,3 +386,25 @@ void __init alloc_intr_gate(unsigned int n, const void *addr) if (!WARN_ON(test_and_set_bit(n, system_vectors))) set_intr_gate(n, addr); } + +void __init early_idt_setup_early_handler(unsigned long physaddr) +{ + gate_desc *idt; + int i; + + idt = fixup_pointer(idt_table, physaddr); + + for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) { + struct idt_data data; + gate_desc desc; + + init_idt_data(&data, i, early_idt_handler_array[i]); + idt_init_desc(&desc, &data); + native_write_idt_entry(idt, i, &desc); + } +} + +void early_load_idt(vo...
2020 Jun 04
0
[PATCH v3 31/75] x86/head/64: Install boot GDT
...0, 0xfffff), +}; + +/* + * Address needs to be set at runtime because it references the boot_gdt while + * the kernel still uses a direct mapping. + */ +struct desc_ptr boot_gdt_descr = { + .size = sizeof(boot_gdt), + .address = 0, +}; + #define __head __section(.head.text) static void __head *fixup_pointer(void *ptr, unsigned long physaddr) diff --git a/arch/x86/kernel/head_64.S b/arch/x86/kernel/head_64.S index 4bbc770af632..62513dd1e0e4 100644 --- a/arch/x86/kernel/head_64.S +++ b/arch/x86/kernel/head_64.S @@ -72,6 +72,26 @@ SYM_CODE_START_NOALIGN(startup_64) /* Set up the stack for verify_cpu(),...
2020 May 18
2
[PATCH v3 31/75] x86/head/64: Install boot GDT
On Tue, Apr 28, 2020 at 05:16:41PM +0200, Joerg Roedel wrote: > @@ -480,6 +500,22 @@ SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) > SYM_DATA(phys_base, .quad 0x0) > EXPORT_SYMBOL(phys_base) > > +/* Boot GDT used when kernel addresses are not mapped yet */ > +SYM_DATA_LOCAL(boot_gdt_descr, .word boot_gdt_end - boot_gdt) >
2020 May 18
2
[PATCH v3 31/75] x86/head/64: Install boot GDT
On Tue, Apr 28, 2020 at 05:16:41PM +0200, Joerg Roedel wrote: > @@ -480,6 +500,22 @@ SYM_DATA_LOCAL(early_gdt_descr_base, .quad INIT_PER_CPU_VAR(gdt_page)) > SYM_DATA(phys_base, .quad 0x0) > EXPORT_SYMBOL(phys_base) > > +/* Boot GDT used when kernel addresses are not mapped yet */ > +SYM_DATA_LOCAL(boot_gdt_descr, .word boot_gdt_end - boot_gdt) >
2020 Aug 24
0
[PATCH v6 70/76] x86/smpboot: Setup TSS for starting AP
...u); load_TR_desc(); /* diff --git a/arch/x86/kernel/head64.c b/arch/x86/kernel/head64.c index ce2d8284edb9..b26a7f1bd6fe 100644 --- a/arch/x86/kernel/head64.c +++ b/arch/x86/kernel/head64.c @@ -545,3 +545,14 @@ void __head startup_64_setup_env(unsigned long physbase) gsbase = (unsigned long)fixup_pointer((void *)initial_gs, physbase); __wrmsr(MSR_GS_BASE, (u32)gsbase, (u32)(gsbase >> 32)); } + +void __head early_load_tss(void) +{ + struct desc_struct *gdt = (struct desc_struct *)early_gdt_descr.address; + tss_desc tss; + + /* Load TSS only if entry in GDT is marked present */ + memcpy(&amp...
2020 Aug 24
96
[PATCH v6 00/76] x86: SEV-ES Guest Support
...data setup out of set_intr_gate() x86/head/64: Install startup GDT x86/head/64: Setup MSR_GS_BASE before calling into C code x86/head/64: Load GDT after switch to virtual addresses x86/head/64: Load segment registers earlier x86/head/64: Switch to initial stack earlier x86/head/64: Make fixup_pointer() static inline x86/head/64: Load IDT earlier x86/head/64: Move early exception dispatch to C code x86/head/64: Set CR4.FSGSBASE early x86/sev-es: Add SEV-ES Feature Detection x86/sev-es: Print SEV-ES info into kernel log x86/sev-es: Compile early handler code into kernel image x86/se...
2020 Jul 24
86
[PATCH v5 00/75] x86: SEV-ES Guest Support
...data setup out of set_intr_gate() x86/head/64: Install startup GDT x86/head/64: Setup MSR_GS_BASE before calling into C code x86/head/64: Load GDT after switch to virtual addresses x86/head/64: Load segment registers earlier x86/head/64: Switch to initial stack earlier x86/head/64: Make fixup_pointer() static inline x86/head/64: Load IDT earlier x86/head/64: Move early exception dispatch to C code x86/head/64: Set CR4.FSGSBASE early x86/sev-es: Add SEV-ES Feature Detection x86/sev-es: Print SEV-ES info into kernel log x86/sev-es: Compile early handler code into kernel image x86/se...
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below the top 2G of the virtual address space. It allows to optionally extend the KASLR randomization range from 1G to 3G. Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler changes, PIE support and KASLR in general. Thanks to
2020 Sep 07
84
[PATCH v7 00/72] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT
2020 Sep 07
84
[PATCH v7 00/72] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de> Hi, here is a new version of the SEV-ES Guest Support patches for x86. The previous versions can be found as a linked list starting here: https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/ I updated the patch-set based on ther review comments I got and the discussions around it. Another important change is that the early IDT