Displaying 3 results from an estimated 3 matches for "fixed_stack7".
2012 Oct 30
1
[LLVMdev] how to define extending vector load patterns?
...; PatFrag, at least. I'd suggest a pattern along the lines of:
>
> (set V2I32Regs:$result, (v2i32 (sextloadvi8 ADDRrr:$address)))
Thanks, now it accepts the pattern, but it still does not work.
LLVM ERROR: Cannot select: 0x1b98410: v2i32,ch = load 0x2bc86a0,
0x1b9d460, 0x25ceb90<LD2[FIXED_STACK7](align=4), sext from v2i8>[ID=365]
2012 Oct 30
2
[LLVMdev] how to define extending vector load patterns?
I have an operation which loads a 16 bit block of data as 2 8-bit
elements, sign extends the both parts to 32 bits and stores the result
into 64-bit vector register.
How can I define the pattern for this?
just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
gives me error that extloav2i8 is not defined.
(the same principle works for scalar sextload)
So I need to define it
2012 Oct 30
0
[LLVMdev] how to define extending vector load patterns?
Hi Heikki,
> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
>
> gives me error that extloav2i8 is not defined.
I don't have a target to test this on, but looking at
include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8"
PatFrag, at least. I'd suggest a pattern along the lines of:
(set V2I32Regs:$result, (v2i32 (sextloadvi8