search for: fisttp

...est.bc yields: .def _main__i__v; .scl 2; .type 32; .endef .text .globl _main__i__v .align 16, 0x90 _main__i__v: # @main__i__v # BB#0: # %locals sub ESP, 20 movss XMM0, DWORD PTR [_t] movss DWORD PTR [ESP + 8], XMM0 fld DWORD PTR [ESP + 8] fisttp QWORD PTR [ESP] mov EAX, DWORD PTR [ESP] mov _x, EAX xor EAX, EAX add ESP, 20 ret .data .globl _t # @t .align 8 _t: .zero 8 .globl _x # @x .align 4 _x: .long 0 # 0x0 Now, the bit I think is wrong is mov _x,EAX I think it should...

Hi, Is there a recommended way to round to the nearest whole (x86 RC field of FPU control = 00) ? It appears an intentional truncation instruction is generated (if ms disassembly is correct): IRBuilder<>::CreateFPToSI %1 = fptosi double %0 to i64 00370025 fisttp qword ptr [esp] Thanks, Bob -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100928/42385881/attachment.html>

...sense; thanks for the tip. Are the getCopyToReg(ST0) and addReg(ST0, ImplicitKill) calls on the expanded MI at all necessary then since X86FloatingPoint seems to manage that all internally? > When SSE is available, x87 registers are only ever used for f80. It looks like it always tries to use fisttp when converting to i64. This bitcode: define i64 @foo(double %x) nounwind readnone { init: %0 = fptosi double %x to i64 ret i64 %0 } gets compiled by LLVM 3.0 to: _foo: # @foo # BB#0: # %init subl $20, %esp movsd 24(%esp), %...

Hi Joe & Michael, In rev. 151382 you have changed the fptoui implementation of the x86 codegen for win32. Before the change fptoui was lowered to flds 16(%esp) fisttpll 8(%esp) movl 8(%esp), %eax After the change fptoui is lowered to flds 40(%esp) calll _ftol2 Please note that the assumption that _ftol2 doesn't modify ECX isn't true on sandybridge platform. Could you share with me the reasons behind this change? Did you get better performan...

On Jan 24, 2012, at 2:30 PM, Joe Groff wrote: > On Fri, Jan 20, 2012 at 2:10 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote: >> X86FloatingPoint.cpp with comments is all you get. > > Thanks for your help, Jakob. Attached is a first-pass attempt at a > patch. I don't want to post to -commits yet because I have no idea if > this is fully correct, but it seems

...t; .endef > .text > .globl _main__i__v > .align 16, 0x90 > _main__i__v:                            # @main__i__v > # BB#0:                                 # %locals > sub ESP, 20 > movss XMM0, DWORD PTR [_t] > movss DWORD PTR [ESP + 8], XMM0 > fld DWORD PTR [ESP + 8] > fisttp QWORD PTR [ESP] > mov EAX, DWORD PTR [ESP] > mov _x, EAX > xor EAX, EAX > add ESP, 20 > ret > > .data > .globl _t                      # @t > .align 8 > _t: > .zero 8 > > .globl _x                      # @x > .align 4 > _x: > .long 0                  ...

...i__v > > .align 16, 0x90 > > _main__i__v: # @main__i__v > > # BB#0: # %locals > > sub ESP, 20 > > movss XMM0, DWORD PTR [_t] > > movss DWORD PTR [ESP + 8], XMM0 > > fld DWORD PTR [ESP + 8] > > fisttp QWORD PTR [ESP] > > mov EAX, DWORD PTR [ESP] > > mov _x, EAX > > xor EAX, EAX > > add ESP, 20 > > ret > > > > .data > > .globl _t # @t > > .align 8 > > _t: > > .zero 8 > > > > .globl _x...

...and -static codegen on Darwin. * Evan added initial support for subtargets in the X86 backend, including a broad range of -mcpu=* values. * Evan improved the loop strength reduction on X86, and it is now turned on by default. * Evan added support for generation of SSE3 instructions (e.g. fisttp) on subtargets that support it. PowerPC-Specific Code Generator Improvements: * Full support for the Altivec instruction set, accessible with the GCC generic vector extension and the altivec.h intrinsics (llvmgcc4 only), including support for -faltivec and -maltivec. * Nate greatly...

...n Darwin. > * Evan added initial support for subtargets in the X86 backend, including > a broad range of -mcpu=* values. > * Evan improved the loop strength reduction on X86, and it is now turned > on by default. > * Evan added support for generation of SSE3 instructions (e.g. fisttp) on > subtargets that support it. > > > PowerPC-Specific Code Generator Improvements: > > * Full support for the Altivec instruction set, accessible with the GCC > generic vector extension and the altivec.h intrinsics (llvmgcc4 only), > including support for -faltivec...

...egen on Darwin. 46. Evan added initial support for subtargets in the X86 backend, including a broad range of -mcpu=* values. 47. Evan improved the loop strength reduction pass on X86, and it is now enabled by default on X86. 48. Evan added support for generation of SSE3 instructions (e.g. fisttp) on subtargets that support it. PowerPC-Specific Code Generator Improvements: 49. The PowerPC backend now includes full support for the Altivec instruction set, accessible with the GCC generic vector extension and the altivec.h intrinsics (llvmgcc4 only), including support for...