Displaying 4 results from an estimated 4 matches for "firstimplicitdef".
2011 Sep 23
2
[LLVMdev] Registers and isel type inference
...known VT, return the VT, otherwise return
/// MVT::Other.
MVT::SimpleValueType CodeGenInstruction::
HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
if (ImplicitDefs.empty()) return MVT::Other;
// Check to see if the first implicit def has a resolvable type.
Record *FirstImplicitDef = ImplicitDefs[0];
assert(FirstImplicitDef->isSubClassOf("Register"));
const std::vector<MVT::SimpleValueType> &RegVTs =
TargetInfo.getRegisterVTs(FirstImplicitDef);
if (RegVTs.size() == 1)
return RegVTs[0];
return MVT::Other;
}
2011 Sep 23
0
[LLVMdev] Registers and isel type inference
Jakob Stoklund Olesen <stoklund at 2pi.dk> writes:
> It appears that tablegen is inferring the 'type' of an individual
> register by enumerating all the register classes it appears in. Some
> things, like using implicit defs in SDNodes, only works for registers
> with a unique type. My WIDE32 class caused GR32 registers to no
> longer have a unique type, breaking
2011 Sep 26
0
[LLVMdev] Registers and isel type inference
...e return
> /// MVT::Other.
> MVT::SimpleValueType CodeGenInstruction::
> HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const {
> if (ImplicitDefs.empty()) return MVT::Other;
>
> // Check to see if the first implicit def has a resolvable type.
> Record *FirstImplicitDef = ImplicitDefs[0];
> assert(FirstImplicitDef->isSubClassOf("Register"));
> const std::vector<MVT::SimpleValueType> &RegVTs =
> TargetInfo.getRegisterVTs(FirstImplicitDef);
> if (RegVTs.size() == 1)
> return RegVTs[0];
> return MVT::Other;
>...
2011 Sep 23
2
[LLVMdev] Registers and isel type inference
So I tried adding a new register class to the x86 target:
def WIDE32 : RegisterClass<"X86", [i32, f32], 32, (add GR32, FR32)>;
I thought this would be a harmless thing to do since the new register class is not being referenced anywhere. I was wrong, it caused all kinds of assertion failures from tablegen's isel pattern generator.
It appears that tablegen is inferring the