search for: finishblock

Displaying 3 results from an estimated 3 matches for "finishblock".

2012 Mar 29
0
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...s to bundling: 1) Bundler operates on a larger scope than the scheduler (preferred): isSchedulingBoundary is true for branches, calls, and other strange barriers. Instructions can be reordered between the boundaries during schedule(), and the bundler can operate across regions via exitRegion() and finishBlock(). You will still have DAG edges from the instruction that a branch depends on to the branch (captured by ExitSU), but you won't have any DAG edges crossing the boundary. 2) Scheduler and bundler operate on the same scope (an entire block): isSchedulingBoundary = false and all instructions mus...
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote: > Tom, > > I do not have your call stack, but packetizer calls > ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is > the first time you use the new MI sched infrastructure (like your target has > not implemented misched yet) there might be some work needed to implement > couple target
2012 Mar 30
1
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...ing: > > 1) Bundler operates on a larger scope than the scheduler (preferred): isSchedulingBoundary is true for branches, calls, and other strange barriers. Instructions can be reordered between the boundaries during schedule(), and the bundler can operate across regions via exitRegion() and finishBlock(). You will still have DAG edges from the instruction that a branch depends on to the branch (captured by ExitSU), but you won't have any DAG edges crossing the boundary. > > 2) Scheduler and bundler operate on the same scope (an entire block): isSchedulingBoundary = false and all instru...