search for: finishbasicblock

...ly impossible), or IR pass must generate only one form, regardless it's FastISel or not. Let's say we take the latter. Since SelectionDAG has only one code path, we must not put too much into the generated IR, because those IR must not get lowered in SelectionDAG SelectBasicBlock() (but in FinishBasicBlock() instead), due to tail call optimization concern. *Conclusion 2*: if we want to keep both tail call optimization and single code path in SelectionDAG, we need to generate trivial IR (declarations for global variables and alloca of canary variable). *Promising Solution*: Generating trivial IR, an...

Hi Ankur, > The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( > "llc -help" doesn't list it ). as far as I remember, displaying DAGs during compilation is only enabled in "debug builds" [1] of LLVM. You probably have to re-configure and re-compile LLVM to enable this feature. Best regards, Christoph [1]

I am trying to understand the SelectionDAG construction from LLVM IR. I have gone through the doc "The LLVM Target-Independent Code Generator" on LLVM site. This gives a great initial overview. However I am unable to catch the actual control flow for the llvm->selectionDag conversion. The flags "-view-sched-dags".. described in the doc doesn't seem to work. ( "llc