Displaying 5 results from an estimated 5 matches for "fhadd".
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2011 Oct 18
0
[LLVMdev] Matching addsub
Hi Hal, you should probably add a target specific DAG combine that
synthesizes the appropriate target instruction. This is how I
handled x86 horizontal add (see the FHADD X86 opcode). If it turns
out that the same thing is useful for other targets then it can be
generalized later.
Ciao, Duncan.
On 10/18/11 00:40, Hal Finkel wrote:
> How should I go about matching floating-point addsub-like vector
> instructions? My first inclination is to write something wh...
2011 Sep 21
2
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from floating
point additions and subtractions of appropriate vector shuffles. To do this I
introduced new x86 FHADD and FHSUB opcodes. These need to be wired up somehow
in the .td file to the appropriate instructions. Since I have no idea how
tablegen works I just hacked it in horribly. It works, but breaks support for
the hadd etc intrinsics (if you take a look at how I did it you will see why!).
I'm sen...
2011 Oct 17
4
[LLVMdev] Matching addsub
How should I go about matching floating-point addsub-like vector
instructions? My first inclination is to write something which matches
build_vector 1.0, -1.0, and then use that in combination with a match on
fadd, but that does not seem to work. I think this is because
BUILD_VECTOR cannot ever be "Legal", and so it is always turned into a
constant load before instruction selection.
2011 Sep 21
0
[LLVMdev] Patch to synthesize x86 hadd instructions; need help with the tablegen bits
Hi Duncan,
On Wed, Sep 21, 2011 at 1:24 PM, Duncan Sands <baldrick at free.fr> wrote:
> This patch synthesizes haddps/haddpd/hsubps/hsubpd instructions from
> floating
> point additions and subtractions of appropriate vector shuffles. To do this
> I
> introduced new x86 FHADD and FHSUB opcodes. These need to be wired up
> somehow
> in the .td file to the appropriate instructions. Since I have no idea how
> tablegen works I just hacked it in horribly. It works, but breaks support
> for
> the hadd etc intrinsics (if you take a look at how I did it you wi...
2011 Oct 18
1
[LLVMdev] Matching addsub
On Tue, 2011-10-18 at 10:51 -0700, Dan Gohman wrote:
> On Oct 17, 2011, at 6:40 PM, Hal Finkel wrote:
>
> > On Mon, 2011-10-17 at 17:33 -0700, Dan Gohman wrote:
> >> On Oct 17, 2011, at 3:40 PM, Hal Finkel wrote:
> >>
> >>> How should I go about matching floating-point addsub-like vector
> >>> instructions? My first inclination is to write