Displaying 2 results from an estimated 2 matches for "ffr1".
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ff01
2012 May 22
2
[LLVMdev] Match operands
...figuration F64 may be either single 64 bit register or a pair of 32 bit registers. In the current implementation this instruction is defined as follows:
// Instructions that convert an FP value to 64-bit fixed point.
let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
multiclass FFR1_L_M<bits<6> funct, string opstr> {
def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
}
// Instructions that convert an FP value to 32-bit fixed point.
multiclass FFR1_W_M<bits<6>...
2012 May 22
0
[LLVMdev] Match operands
...e either single 64 bit register or a pair of 32 bit registers. In the current implementation this instruction is defined as follows:
>
> // Instructions that convert an FP value to 64-bit fixed point.
> let Predicates = [IsFP64bit], DecoderNamespace = "Mips64" in
> multiclass FFR1_L_M<bits<6> funct, string opstr> {
> def _S : FFR1<funct, 16, opstr, "l.s", FGR64, FGR32>;
> def _D64 : FFR1<funct, 17, opstr, "l.d", FGR64, FGR64>;
> }
>
> // Instructions that convert an FP value to 32-bit fixed point.
> multicl...