Displaying 20 results from an estimated 33 matches for "fetchsrc".
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fetcher
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...POW:
> case TGSI_OPCODE_SHL:
> case TGSI_OPCODE_ISHR:
> case TGSI_OPCODE_USHR:
> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
> break;
> + case TGSI_OPCODE_POW:
> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
> + break;
Can you use mkMov ? Pretty...
2015 Feb 20
10
[PATCH 01/11] nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmax
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 66 +++++++++++++++++++++-
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
index dfb093c..e38a3b8 100644
---
2014 May 21
2
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...>> case TGSI_OPCODE_ISHR:
>>> case TGSI_OPCODE_USHR:
>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>> break;
>>> + case TGSI_OPCODE_POW:
>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
>&g...
2016 Apr 21
3
[PATCH mesa v2 1/3] nouveau: codegen: LOAD: Always use component 0 when getting the address
..._tgsi.cpp
index 557608e..d3c2d61 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2277,7 +2277,7 @@ Converter::handleLOAD(Value *dst0[4])
if (!dst0[c])
continue;
- Value *off = fetchSrc(1, c);
+ Value *off = fetchSrc(1, 0);
Symbol *sym;
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
--
2.7.3
2014 May 20
0
[PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...CODE_OR:
- case TGSI_OPCODE_POW:
case TGSI_OPCODE_SHL:
case TGSI_OPCODE_ISHR:
case TGSI_OPCODE_USHR:
@@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
break;
+ case TGSI_OPCODE_POW:
+ val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
+ FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
+ mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
+ break;
case TGSI_OPCODE_EX2:
case TGSI_OPCODE_LG2:...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...GSI_OPCODE_SHL:
>> case TGSI_OPCODE_ISHR:
>> case TGSI_OPCODE_USHR:
>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>> break;
>> + case TGSI_OPCODE_POW:
>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>> + mkOp1(OP_MOV, TYPE_F32, dst0[c], val0);
>> + break;
>...
2014 May 21
0
[Mesa-dev] [PATCH 04/12] nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
...e TGSI_OPCODE_ISHR:
>>>> case TGSI_OPCODE_USHR:
>>>> @@ -2254,6 +2253,11 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> mkOp1(OP_MOV, TYPE_U32, dst0[c], fetchSrc(0, c));
>>>> break;
>>>> + case TGSI_OPCODE_POW:
>>>> + val0 = mkOp2v(op, TYPE_F32, getScratch(), fetchSrc(0, 0), fetchSrc(1, 0));
>>>> + FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi)
>>>> + mkOp1(OP_MOV, TYPE_F32, ds...
2014 May 20
14
[PATCH 00/12] Cherry-pick nv50/nvc0 patches from gallium-nine
I went through the gallium-nine tree and picked out nouveau patches that are
general bug-fixes. The first bunch I'd like to also get into 10.2. I've
reviewed all of them and they make sense to me, but sending them out for
public review as well in case there are any objections.
Unless I hear objections, I'd like to push this by Friday.
Christoph Bumiller (11):
nv50,nvc0: always pull
2016 Apr 08
2
[PATCH] nouveau: codegen: Take src swizzle into account on loads
Hi,
On 08-04-16 17:45, Ilia Mirkin wrote:
> On Fri, Apr 8, 2016 at 11:28 AM, Hans de Goede <hdegoede at redhat.com> wrote:
>> When dealing with non vector variables the llvm register allocator
>> will use TEMP[0].x then TEMP[0].y, etc.
>>
>> When loading something from a global buffer it will calculate the
>> address to use, and store that in say TEMP[0].x,
2016 Apr 08
0
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...RE already takes swizzling
> into account, so the proposed option 2 will actually make the 2 more inline.
Erm, I mean the 2nd src operand of the store of-course, the actual src.
On a related note, comparing handleLOAD and handleSTORE, this bit in
handleLOAD seems wrong:
Value *off = fetchSrc(1, c);
I believe that should be:
Value *off = fetchSrc(1, 0);
Just like handleSTORE does:
off = fetchSrc(0, 0);
And always using a 'c' of 0 seems correct here since we are dealing
with an address.
Once I know which docs to update for this, I'll do a v2 of this patch
and add a...
2014 Nov 18
2
[PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...u/codegen/nv50_ir_from_tgsi.cpp
index 41b91e8..e5b767f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
src0 = fetchSrc(0, c);
val0 = getScratch();
mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
- mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
+ mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
+ mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
}
break;
case TGSI_OPCODE_ROUND:
--...
2016 Apr 07
2
[PATCH] nouveau: codegen: Take src swizzle into account on loads
.../gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 557608e..cc51f5a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
Value *off = fetchSrc(1, c);
Symbol *sym;
+ uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
+
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
- tgsi.getSr...
2016 Mar 16
2
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...UFFER:
> + case TGSI_FILE_MEMORY:
> for (c = 0; c < 4; ++c) {
> if (!dst0[c])
> continue;
> @@ -2295,9 +2300,12 @@ Converter::handleLOAD(Value *dst0[4])
> if (tgsi.getSrc(0).isIndirect(0))
> ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
> }
> - return;
> + break;
> + default:
> + assert(!"Unsupported srcFile for LOAD");
> }
>
> +/* Keep this around for now as reference when adding img support
> getResourceCoords(off, r, 1...
2014 Nov 18
2
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...x 41b91e8..e5b767f 100644
>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>> src0 = fetchSrc(0, c);
>> val0 = getScratch();
>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>> + mkOp1(OP_SAT, TYPE_F32, dst0[c], val0);
>>...
2014 Jan 13
20
[PATCH 00/19] nv50: add sampler2DMS/GP support to get OpenGL 3.2
OK, so there's a bunch of stuff in here. The geometry stuff is based on the
work started by Bryan Cain and Christoph Bumiller.
Patches 01-12: Add support for geometry shaders and fix related issues
Patches 13-14: Make it possible for fb clears to operate on texture attachments
with an explicit layer set (as is allowed in gl 3.2).
Patches 15-17: Make ARB_texture_multisample work
2016 Jan 14
0
[PATCH] nv50/ir: rebase indirect temp arrays to 0, so that we use less lmem space
...p;idx2d) const
+{
+ std::map<int, tgsi::Source::TempBase>::const_iterator it =
+ code->indirectTempBases.find(arrayId);
+ if (it == code->indirectTempBases.end())
+ return;
+
+ idx2d = 1;
+ idx += it->second.newBase - it->second.oldBase;
+}
+
Value *
Converter::fetchSrc(tgsi::Instruction::SrcRegister src, int c, Value *ptr)
{
int idx2d = src.is2D() ? src.getIndex(1) : 0;
- const int idx = src.getIndex(0);
+ int idx = src.getIndex(0);
const int swz = src.getSwizzle(c);
Instruction *ld;
@@ -1728,8 +1759,7 @@ Converter::fetchSrc(tgsi::Instruction::...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...Src(0).getFile()) {
+ case TGSI_FILE_BUFFER:
+ case TGSI_FILE_MEMORY:
for (c = 0; c < 4; ++c) {
if (!dst0[c])
continue;
@@ -2295,9 +2300,12 @@ Converter::handleLOAD(Value *dst0[4])
if (tgsi.getSrc(0).isIndirect(0))
ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
}
- return;
+ break;
+ default:
+ assert(!"Unsupported srcFile for LOAD");
}
+/* Keep this around for now as reference when adding img support
getResourceCoords(off, r, 1);
if (isResourceRaw(code, r)) {
@@ -236...
2014 Nov 18
1
[Mesa-dev] [PATCH] nv50/ir: saturate FRC result to avoid completely bogus values
...;>> --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>>>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>>>> @@ -2512,7 +2512,8 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
>>>> src0 = fetchSrc(0, c);
>>>> val0 = getScratch();
>>>> mkOp1(OP_FLOOR, TYPE_F32, val0, src0);
>>>> - mkOp2(OP_SUB, TYPE_F32, dst0[c], src0, val0);
>>>> + mkOp2(OP_SUB, TYPE_F32, val0, src0, val0);
>>>> + mkOp1(...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...I_FILE_MEMORY:
>> for (c = 0; c < 4; ++c) {
>> if (!dst0[c])
>> continue;
>> @@ -2295,9 +2300,12 @@ Converter::handleLOAD(Value *dst0[4])
>> if (tgsi.getSrc(0).isIndirect(0))
>> ld->setIndirect(0, 1, fetchSrc(tgsi.getSrc(0).getIndirect(0), 0, 0));
>> }
>> - return;
>> + break;
>> + default:
>> + assert(!"Unsupported srcFile for LOAD");
>> }
>>
>> +/* Keep this around for now as reference when adding img support
>&...
2014 Jun 23
1
[PATCH] nv50/ir: make ARB_viewport_array behave like it does with other drivers
...mkStore(OP_EXPORT, TYPE_U32, dstToSym(dst, c), ptr, val);
+ }
} else
if (f == TGSI_FILE_TEMPORARY ||
f == TGSI_FILE_PREDICATE ||
@@ -2523,6 +2535,14 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn)
mkCvt(OP_CVT, dstTy, dst0[c], srcTy, fetchSrc(0, c));
break;
case TGSI_OPCODE_EMIT:
+ /* export the saved viewport index */
+ if (viewport != NULL) {
+ Symbol *VPSym = mkSymbol(FILE_SHADER_OUTPUT, info->io.viewportID,
+ TYPE_U32,
+ info->out[in...