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...hese semantics, while the L/S membars are offered to varying levels of detail on several architectures. As Itanium is not yet a fully functional target, it was not prioritized. Moreover, as the only instructions (to my knowledge) on Itanium to have memory synchronization components are cmpxchg and fetchadd, these could be implemented correctly when implementing the lowering for the instructions in this proposal, while still providing full memory barriers when needed outside of the atomic instructions. If there is serious demand for building memory semantics into the atomic instructions, "aquire&...

On Monday 09 July 2007 19:33, Scott Michel wrote: > Torvald Riegel wrote: > > Hi, > > > > I'd like to see support for something like this. I have some comments, > > and I think there is existing work that you can reuse. > > "reuse within the compiler." within the LLVM compiler framework, to be precise. > > > "While the processor may

Torvald Riegel wrote: > Hi, > > I'd like to see support for something like this. I have some comments, and I > think there is existing work that you can reuse. "reuse within the compiler." > "While the processor may spin and attempt the atomic operation more than once > before it is successful, research indicates this is extremely uncommon." > I