Displaying 5 results from an estimated 5 matches for "fegetexceptflag".
2013 Mar 01
3
[LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
...1 of them are compile stage failures
===
MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
the reason is tilegx do not support some c99 float
rounding & exceptions
we lack the support of some flag like FE_DIVBYZERO
etc, for fegetexceptflag.
16 of them are runtime failures.
===
actually, I compare all these failures with our gcc
output, it's the same.
nearly all of them are caused by float point
precision issue, for example,
MultiSource/Applications/sqlite3/
....
2013 Mar 01
0
[LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
...> test-suite (17 failures)
> ======
> 1 of them are compile stage failures
> ===
> MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
> the reason is tilegx do not support some c99 float rounding &
> exceptions
> we lack the support of some flag like FE_DIVBYZERO etc, for
> fegetexceptflag.
>
> 16 of them are runtime failures.
> ===
> actually, I compare all these failures with our gcc output, it's the
> same.
> nearly all of them are caused by float point precision issue, for
> example,
>
> MultiSource/Applications/sqlite3/
> ...
> 6|496148.33...
2013 Mar 01
0
[LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
----- Original Message -----
> From: "Jiong Wang" <jiwang at tilera.com>
> To: "LLVM Developers Mailing List" <llvmdev at cs.uiuc.edu>, cfe-dev at cs.uiuc.edu
> Sent: Thursday, February 28, 2013 6:09:20 PM
> Subject: [LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
>
> Hi,
>
> On behalf of Tilera Corporation,
2013 Mar 01
2
[LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
...t;> ======
>> 1 of them are compile stage failures
>> ===
>> MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
>> the reason is tilegx do not support some c99 float rounding &
>> exceptions
>> we lack the support of some flag like FE_DIVBYZERO etc, for
>> fegetexceptflag.
>>
>> 16 of them are runtime failures.
>> ===
>> actually, I compare all these failures with our gcc output, it's the
>> same.
>> nearly all of them are caused by float point precision issue, for
>> example,
>>
>> MultiSource/Applications/s...
2013 Mar 01
2
[LLVMdev] RFC: TileGX, a new backend for Tilera's many core processor
Hi,
On behalf of Tilera Corporation, I'd like to contribute llvm ports to
Tilera's TILE-Gx
architecture and wish this could be submitted to main llvm tree.
TILE-Gx is a VLIW architecture with 64-bit registers, 64-bit address space,
and 64-bit instructions. TILE-Gx has load-store architecture ISAs.
More information on the architectures is available at