search for: febd6000

...er+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at c060 [size=32] Region 1: Memory at febd6000 (32-bit, non-prefetchable) [size=4K] Region 2: Memory at fea00000 (32-bit, non-prefetchable) [size=512K] Expansion ROM at feb80000 [disabled] [size=256K] Capabilities: [84] MSI-X: Enable+ Count=3 Masked- Vector table: BAR=1 offset=00000000 PBA: BAR=1 offset=00000800 Capabilities: [70] VirtI...

...er+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Interrupt: pin A routed to IRQ 10 Region 0: I/O ports at c060 [size=32] Region 1: Memory at febd6000 (32-bit, non-prefetchable) [size=4K] Region 2: Memory at fea00000 (32-bit, non-prefetchable) [size=512K] Expansion ROM at feb80000 [disabled] [size=256K] Capabilities: [84] MSI-X: Enable+ Count=3 Masked- Vector table: BAR=1 offset=00000000 PBA: BAR=1 offset=00000800 Capabilities: [70] VirtI...

virtio uses vendor-specific capabilities to specify the location of the virtio register ranges. The specification can be found here: http://docs.oasis-open.org/virtio/virtio/v1.0/cs01/virtio-v1.0-cs01.html#x1-690004 This patch adds support for decoding these capabilities to lspci. Signed-off-by: Gerd Hoffmann <kraxel at redhat.com> --- Makefile | 2 +- ls-caps-vendor.c | 76

virtio uses vendor-specific capabilities to specify the location of the virtio register ranges. The specification can be found here: http://docs.oasis-open.org/virtio/virtio/v1.0/cs01/virtio-v1.0-cs01.html#x1-690004 This patch adds support for decoding these capabilities to lspci. Signed-off-by: Gerd Hoffmann <kraxel at redhat.com> --- Makefile | 2 +- ls-caps-vendor.c | 76