Displaying 2 results from an estimated 2 matches for "featureymm".
2009 Apr 30
2
[LLVMdev] RFC: AVX Feature Specification
...39;s the first one.
In some ways AVX is "just another" SSE level. Having AVX implies you have
SSE1-SSE4.2. However AVX is very different from SSE and there are a number
of sub-features which may or may not be available on various implementations.
So right now I've done this:
def FeatureYMM : SubtargetFeature<"ymm", "X86YMM", "true", // Cray
"Enable YMM state">;
def FeatureVEX : SubtargetFeature<"vex", "X86VEX", "true", // Cray...
2009 Apr 30
0
[LLVMdev] RFC: AVX Feature Specification
...ust another" SSE level. Having AVX implies
> you have
> SSE1-SSE4.2. However AVX is very different from SSE and there are a
> number
> of sub-features which may or may not be available on various
> implementations.
>
> So right now I've done this:
>
> def FeatureYMM : SubtargetFeature<"ymm", "X86YMM", "true", // Cray
> "Enable YMM state">;
> def FeatureVEX : SubtargetFeature<"vex", "X86VEX", "true", // Cray
>...