Displaying 4 results from an estimated 4 matches for "featureneon".
2009 Nov 22
2
[LLVMdev] arm cortex-m3
Here is a one-line patch to support the cortex-m3.
For those who plan the features for ARM, the new cortex-m0 implements
only a subset of the Thumb2 instructions. I still have yet to see a
document that details what's in the subset.
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2009 Nov 24
0
[LLVMdev] arm cortex-m3
...RM.td
> ===================================================================
> --- ARM.td (revision 89605)
> +++ ARM.td (working copy)
> @@ -106,6 +106,7 @@
> def : Processor<"cortex-a8", CortexA8Itineraries,
> [ArchV7A, FeatureThumb2, FeatureNEON]>;
> def : ProcNoItin<"cortex-a9", [ArchV7A, FeatureThumb2, FeatureNEON]>;
> +def : ProcNoItin<"cortex-m3", [ArchV7A, FeatureThumb2]>;
>
> //===----------------------------------------------------------------------===//
> // Register...
2016 Dec 16
1
help/hints/suggestions/tips please: how to give _generic_ compilation for a particular ISA a non-zero LoopMicroOpBufferSize?
...NoSchedModel" seems to be generated from this TableGen code in the source-tree file
at "llvm/lib/Target/AArch64/AArch64.td":
def : ProcessorModel<"generic", NoSchedModel, [
FeatureCRC,
FeatureFPARMv8,
FeatureNEON,
FeaturePerfMon,
FeaturePostRAScheduler
]>;
... wherein it`s obvious how to add something like "FeatureCustomCheapAsMoveHandling" to the
list of features, but I have no idea how to change the LoopMicroOpBufferSize, def...
2015 Sep 15
3
The Trouble with Triples
On 15 September 2015 at 19:34, Daniel Sanders <Daniel.Sanders at imgtec.com> wrote:
> We can go further with this analogy too. For example, let's say John Smith
> with the SSN Y also answers to the name Rameses. This is the problem that
> Renato is working on. Renato needs to be able to see the name Rameses and
> map this to the correct John Smith (or at least someone very