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7dc2ec7
2011 Apr 06
1
[LLVMdev] Adding scheduling constraints to intrinsics
Hi,
I am working on fixing a bug in the x86 codegen and I need help in adding a new type of scheduling constraints.
The bug I am fixing is related to SSE instruction scheduling. SSE instructions use the "mxcsr" register for selecting the desired rounding mode. This control register is set/read by an intrinsic. Currently, this intrinsic has no scheduling deps and SSE instructions are