search for: fastmult

...aw in the post: http://lists.xiph.org/pipermail/speex-dev/2005-June/003485.html that this version of speex works fine on ARM platforms. My configuration is: # cat /proc/cpuinfo Processor : ARM926EJ-Sid(wb) rev 3 (v5l) BogoMIPS : 95.83 (about 192 MHz) Features : swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant : 0x0 CPU part : 0x926 CPU revision : 3 Cache type : write-back Cache clean : cp15 c7 ops Cache lockdown : format C Cache format : Harvard # gcc --version arm-linux-gcc (GCC) 3.3.2 (Debian) Configurati...

...armv7l-unknown-linux-gnueabihf --target=armv7l-unknown-linux-gnueabihf --with-cpu=cortex-a9 --with-fpu=neon --with-float=hard --enable-optimized $ cat /proc/cpuinfo Processor : ARMv7 Processor rev 0 (v7l) processor : 0 BogoMIPS : 1992.29 processor : 1 BogoMIPS : 1992.29 Features : swp half thumb fastmult vfp edsp vfpv3 vfpv3d16 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x1 CPU part : 0xc09 CPU revision : 0 Any ideas? Dmitri -- main(i,j){for(i=2;;i++){for(j=2;j<i;j++){if(!(i%j)){j=0;break;}}if (j){printf("%d\n",i);}}} /*Dmitri Gribenko <gribozavr at gmail.com>*/

...03485.html > > that this version of speex works fine on ARM platforms. My configuration > > is: > > > > # cat /proc/cpuinfo > > Processor : ARM926EJ-Sid(wb) rev 3 (v5l) > > BogoMIPS : 95.83 (about 192 MHz) > > Features : swp half thumb fastmult edsp java > > CPU implementer : 0x41 > > CPU architecture: 5TEJ > > CPU variant : 0x0 > > CPU part : 0x926 > > CPU revision : 3 > > Cache type : write-back > > Cache clean : cp15 c7 ops > > Cache lockdown : format C > > C...

The following failures are consistent on buildbot (and my local box). The Clang one I think it's assuming an Intel box, the other two look like the FileCheck are not good enough. http://lab.llvm.org:8011/builders/clang-native-arm-cortex-a9/builds/4305 Clang :: CodeGen/compound-assign-overflow.c LLVM :: Transforms/LoopStrengthReduce/post-inc-icmpzero.ll LLVM ::

Hi Linfeng, On 06/06/17 04:09 PM, Jonathan Lennox wrote: > Two comments on the various infrastructure for RTCD etc. > > 1. The 0002- patch changes the ABI of the celt_pitch_xcorr functions, > but doesn’t change the assembly in celt/arm/celt_pitch_xcorr_arm.s > correspondingly. I suspect the ‘arch’ parameter can just be ignored > by the assembly functions, but at least the

...n you paste the result of a "clang -v -mcpu=CPU file.c" on your box? I > want to see what are the arguments and the assembler/linker it's > choosing to use. What CPU are we talking about? The box itself is an Allwinner A10; armv7l. /proc/cpuinfo says it's got swp half thumb fastmult vfp edsp neon vfpv3. I've been unable to find any values for CPU which are accepted (it just says 'unknown target CPU'. I've tried arm, armv7, armv7a, armv7l, arm7, armv4t... Any suggestions? Is there a way to get clang and llc to emit a list of what triples they support? Since I...

...rg/pipermail/speex-dev/2005-June/003485.html > that this version of speex works fine on ARM platforms. My configuration > is: > > # cat /proc/cpuinfo > Processor : ARM926EJ-Sid(wb) rev 3 (v5l) > BogoMIPS : 95.83 (about 192 MHz) > Features : swp half thumb fastmult edsp java > CPU implementer : 0x41 > CPU architecture: 5TEJ > CPU variant : 0x0 > CPU part : 0x926 > CPU revision : 3 > Cache type : write-back > Cache clean : cp15 c7 ops > Cache lockdown : format C > Cache format : Harvard > > # gcc --...

...to deploy theora in Fressacle iMX27 (ARM-9) processor. This hardware does not support floating point operations, i've compiled the libtheora with ?--disable-float option . mx27# cat /proc/cpuinfo Processor ? ? ? : ARM926EJ-S rev 4 (v5l) BogoMIPS ? ? ? ?: 199.06 Features ? ? ? ?: swp half thumb fastmult edsp java CPU implementer : 0x41 CPU architecture: 5TEJ CPU variant ? ? : 0x0 CPU part ? ? ? ?: 0x926 CPU revision ? ?: 4 Cache type ? ? ?: write-back Cache clean ? ? : cp15 c7 ops Cache lockdown ?: format C Cache format ? ?: Harvard I size ? ? ? ? ?: 16384 I assoc ? ? ? ? : 4 I line length ? : 32...

I saw in the anouncement for the upcoming Boston, MA conference that there will be demos of CentOS on an ARM7 system. I am wondering: does this mean that there is somewhere out there a build of some version of CentOS that might run on a Raspberry Pi (which has an ARM7 processor)? -- Robert Heller -- 978-544-6933 Deepwoods Software -- Custom Software Services

Thank Jonathan and Jean-Marc! I attached the new patch sets in inner_prod_5patches_v3.zip. The Chromebook I'm using is Chromebook 13 CB5-311 series RMN: Z3ENN CPU info: $ cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 2.31 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part : 0xc0f CPU revision : 3 Hardware : NVIDIA Tegra SoC (Flattened Device Tree) Revision : 0000 Serial : 0000000000000000 Thanks, Linfeng On Tue, Jun 6, 2017 at 1:15 P...

In the past 24 hours multiple persons have contacted me regarding the use of elliptic curve cryptography in tinc 1.1 in light of the suspicion that the NSA might have weakened algorithms and/or elliptic curves published by NIST. The new protocol in tinc 1.1 (SPTPS) uses ECDH and ECDSA to do session key exchange and authentication, in such a way that it has the perfect forward secrecy (PFS)

In the past 24 hours multiple persons have contacted me regarding the use of elliptic curve cryptography in tinc 1.1 in light of the suspicion that the NSA might have weakened algorithms and/or elliptic curves published by NIST. The new protocol in tinc 1.1 (SPTPS) uses ECDH and ECDSA to do session key exchange and authentication, in such a way that it has the perfect forward secrecy (PFS)

On 8 February 2013 21:42, David Given <dg at cowlark.com> wrote: > The box itself is an Allwinner A10; armv7l. /proc/cpuinfo says it's got > swp half thumb fastmult vfp edsp neon vfpv3. > Yes, it's a Cortex-A8. I've been unable to find any values for CPU which are accepted (it just > says 'unknown target CPU'. I've tried arm, armv7, armv7a, armv7l, arm7, > armv4t... Any suggestions? Is there a way to get clang and llc to emit a...

...=armv7l-unknown-linux-gnueabihf --with-cpu=cortex-a9 --with-fpu=neon --with-float=hard --enable-optimized $ cat /proc/cpuinfo Processor : ARMv7 Processor rev 0 (v7l) processor : 0 BogoMIPS : 1992.29 processor : 1 BogoMIPS : 1992.29 Features : swp half thumb fastmult vfp edsp vfpv3 vfpv3d16 CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x1 CPU part : 0xc09 CPU revision : 0 Any ideas? Dmitri -- main(i,j){for(i=2;;i++){for(j=2;j<i;j++){if(!(i%j)){j=0;break;}}if (j){printf("%d\n",i);}}} /*Dmitri Gribenko <gribozavr at gm...

On 8 February 2013 14:28, David Given <dg at cowlark.com> wrote: > Debian's clang packages are totally broken on armhf --- the compiler > emits a confused warning about the platform being unrecognised, and then > generates softfloat code --- so I was wondering about LLVM itself. I'm using Ubuntu on Pandas and Chromebooks and LLVM itself behaves well, with the right set of

...list: 0 Thread(s) per core: 1 Core(s) per socket: 1 Socket(s): 1 Vendor ID: ARM Model: 7 Model name: ARM1176 Stepping: r0p7 CPU max MHz: 700.0000 CPU min MHz: 700.0000 BogoMIPS: 697.95 Flags: half thumb fastmult vfp edsp java tls $ dovecot -n: # 2.3.7 (494d20bdc): /etc/dovecot/dovecot.conf # OS: Linux 4.14.50-2-ARCH armv6l # Hostname: alarmpi doveconf: Error: t_readlink(/var/run/dovecot/dovecot.conf) failed: readlink() failed: No such file or directory namespace { inbox = yes location = mailbox {...

Renato Golin wrote: [...] > Try setting armv7a-unknown-linux-gnueabihf and see if it works better. No, that doesn't work either. [...] > JIT was never the forte of ARM and I haven't tried yet, but I doubt > it'll be any Debian misconfiguration. The whole architecture > configuration is a bit odd... Debian's clang packages are totally broken on armhf --- the compiler