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Thanks Michael and Dibyendu for doing the experimentation and bringing this up to our attention. It might be the case what Matt described here. I will take a look at it. Farhana From: Michael Kuperstein [mailto:mkuper at google.com] Sent: Wednesday, December 14, 2016 9:56 AM To: Das, Dibyendu <Dibyendu.Das at amd.com>; Aleen, Farhana A <farhana.a.aleen at intel.com> Cc: Matthew Simpson <mssimpso at codeaurora.org>; llvm-dev at lists.llvm.org Subject: Re:...

...it is - that is a known issue in the x86 cost model. Vectorizing interleaved memory accesses on x86 was, until recently, disabled by default. It's been enabled since r284779, but the cost model is very conservative, and basically assumes we're going to scalarize interleaved ops. I believe Farhana is working on improving that. Michael On Wed, Dec 14, 2016 at 8:44 AM, Das, Dibyendu <Dibyendu.Das at amd.com> wrote: > Hi Matt- > > > > Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and > Intel ). > > > > -dibyendu > > > > *...

...the x86 cost model. > > Vectorizing interleaved memory accesses on x86 was, until recently, > disabled by default. It's been enabled since r284779, but the cost model is > very conservative, and basically assumes we're going to scalarize > interleaved ops. > > I believe Farhana is working on improving that. > > Michael > > > On Wed, Dec 14, 2016 at 8:44 AM, Das, Dibyendu <Dibyendu.Das at amd.com> > wrote: > >> Hi Matt- >> >> >> >> Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and >> Intel...

Hi Matt- Yeah I used a pretty recent llvm (post 3.9) on an x86-64 ( both AMD and Intel ). -dibyendu From: Matthew Simpson [mailto:mssimpso at codeaurora.org] Sent: Wednesday, December 14, 2016 10:03 PM To: Das, Dibyendu <Dibyendu.Das at amd.com> Cc: Michael Kuperstein <mkuper at google.com>; llvm-dev at lists.llvm.org Subject: Re: [llvm-dev] Enabling scalarized conditional stores in