Displaying 20 results from an estimated 22 matches for "falseval".
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falsevalue
2013 May 13
3
[LLVMdev] Q: When is a boolean not a boolean?
...ent();
bool Changed = false;
- Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext());
+ Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext());
BasicBlockEdge TrueE(Parent, TrueSucc);
Changed |= propagateEquality(BranchCond, TrueVal, TrueE);
- Value *FalseVal = ConstantInt::getFalse(FalseSucc->getContext());
+ Value *FalseVal = ConstantInt::getFalse(BranchCond->getContext());
BasicBlockEdge FalseE(Parent, FalseSucc);
Changed |= propagateEquality(BranchCond, FalseVal, FalseE);
Any other ideas about where I should look for the root pro...
2007 Oct 26
2
[LLVMdev] LLVM Newbie. Questions about backend.
...een studying LLVM and started to create a new backend for a
new RISC architecture. Now I need some help to get forward with my
project. I'm quite new to compiling techniques so I'm sorry for the
stupid questions.
Question 1:
My idea is to lower the select SDNode as follows:
%res1 = %falseVal
%res2 = setc %trueVal, %condition
Where setc is conditional mov. The question is how can I make sure
that %res1 and %res2 are assigned to the same phsyical register? (I'm
assuming you can only define virtual register once, is this correct
assumption?)
Question 2:
What kind of informatio...
2013 May 13
0
[LLVMdev] Q: When is a boolean not a boolean?
...gt;
> - Value *TrueVal = ConstantInt::getTrue(TrueSucc->getContext());
> + Value *TrueVal = ConstantInt::getTrue(BranchCond->getContext());
> BasicBlockEdge TrueE(Parent, TrueSucc);
> Changed |= propagateEquality(BranchCond, TrueVal, TrueE);
>
> - Value *FalseVal = ConstantInt::getFalse(FalseSucc->getContext());
> + Value *FalseVal = ConstantInt::getFalse(BranchCond->getContext());
> BasicBlockEdge FalseE(Parent, FalseSucc);
> Changed |= propagateEquality(BranchCond, FalseVal, FalseE);
>
> Any other ideas about where I sh...
2012 Aug 19
1
[LLVMdev] MBlaze select_cc lowering question.
...::EmitCustomSelect.
> SDValue MBlazeTargetLowering::LowerSELECT_CC(SDValue Op,
> SelectionDAG &DAG) const {
> SDValue LHS = Op.getOperand(0);
> SDValue RHS = Op.getOperand(1);
> SDValue TrueVal = Op.getOperand(2);
> SDValue FalseVal = Op.getOperand(3);
> DebugLoc dl = Op.getDebugLoc();
> unsigned Opc;
>
> SDValue CompareFlag;
> if (LHS.getValueType() == MVT::i32) {
> Opc = MBlazeISD::Select_CC;
> CompareFlag = DAG.getNode(MBlazeISD::ICmp, dl, MVT::i32, LHS, RHS)
> .ge...
2006 Aug 21
5
[LLVMdev] selecting select_cc
I am trying to add support for select_cc. In ARM it can be implemented with:
mov $dst, $falseVal
cmp $a, $b
moveq $dst, $trueVal
My current strategy is to expand select_cc in two ARM nodes:
ARM::SELECT and ARM::CMP. The two nodes would be connected by a flag
edge.
ARM::CMP would then expand to "cmp $a, $b". This instruction has no
results. It only alters the CPSR (current program...
2006 Aug 22
0
[LLVMdev] selecting select_cc
Hi Rafael,
> I am trying to add support for select_cc. In ARM it can be implemented
> with:
>
> mov $dst, $falseVal
> cmp $a, $b
> moveq $dst, $trueVal
The more normal ARM code, as produced by assembly writers and compilers
that I've seen, is
cmp $a, $b
moveq $dst, $trueVal
movne $dst, $falseVal
e.g. at the end of a function returning r0
orr r0, r0, #0x40
cmp r0, #0xfe
moveq...
2008 Sep 12
2
[LLVMdev] Selection Condition Codes
...t to do is turn this into
// a series of instructions that in the end become a compare
// and a cmov_logical
{
MachineOperand Dst = MI->getOperand(0);
MachineOperand TrueVal = MI->getOperand(1);
MachineOperand FalseVal = MI->getOperand(2);
MachineOperand CCFlag = MI->getOperand(3);
CC = (INSTCC::CondCodes)MI->getOperand(3).getImm();
// Here I want to get the destination register
of SET_CC instruction and place it as the first addReg
TODO(Get setcc destin...
2008 Sep 12
0
[LLVMdev] Selection Condition Codes
On Thu, Sep 11, 2008 at 6:14 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote:
> I am attempting to lower the selectCC instruction to the instruction set of
> the backend I'm working on and I cannot seem to find a way to correctly
> implement this instruction. I know how this instruction should get
> implemented; I just have yet to find a way to do it. I want the select_cc
2016 Jul 20
2
Hitting assertion failure related to vectorization + instcombine
...tate -loop-vectorize -instcombine
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'Combine redundant instructions' on function '@strsave'
---
Looking at the code, the issue is with this line:
if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C))) &&
*Y == ~*C)
In this case Y is a 128-bit APInt, and so is the value that C is extracted from, but the m_APInt matcher has code that calls getSplatValue() if the matched expression has vector type. So C ends up as an 8-bit value, triggering the as...
2016 Jul 20
2
Hitting assertion failure related to vectorization + instcombine
...tion Pass Manager' on module '<stdin>'.
>> 2. Running pass 'Combine redundant instructions' on function '@strsave'
>>
>> ---
>>
>> Looking at the code, the issue is with this line:
>>
>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C))) &&
>> *Y == ~*C)
>>
>> In this case Y is a 128-bit APInt, and so is the value that C is
>> extracted from, but the m_APInt matcher has code that calls getSplatValue()
>> if the matched expression has vector type. So C...
2008 Sep 12
2
[LLVMdev] Selection Condition Codes
I am attempting to lower the selectCC instruction to the instruction set
of the backend I'm working on and I cannot seem to find a way to
correctly implement this instruction. I know how this instruction should
get implemented; I just have yet to find a way to do it. I want the
select_cc instruction to be lowered into a comparison followed by a
conditional move. I've attempted to use a
2016 Jul 22
2
Hitting assertion failure related to vectorization + instcombine
....
>>>> 2. Running pass 'Combine redundant instructions' on function '@strsave'
>>>>
>>>> ---
>>>>
>>>> Looking at the code, the issue is with this line:
>>>>
>>>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X), m_APInt(C)))
>>>> &&
>>>> *Y == ~*C)
>>>>
>>>> In this case Y is a 128-bit APInt, and so is the value that C is
>>>> extracted from, but the m_APInt matcher has code that calls getSplatValue()
>>...
2016 Jul 25
2
Hitting assertion failure related to vectorization + instcombine
...function
>> >>>> '@strsave'
>> >>>>
>> >>>> ---
>> >>>>
>> >>>> Looking at the code, the issue is with this line:
>> >>>>
>> >>>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X),
>> >>>> m_APInt(C)))
>> >>>> &&
>> >>>> *Y == ~*C)
>> >>>>
>> >>>> In this case Y is a 128-bit APInt, and so is the value that C is
>> >>>> extracted fro...
2012 Nov 17
0
[LLVMdev] Question about lowering clamp function to bic/usat on ARM
Hi,
Given a function like x < 0 ? 0 : x
We can lower it to bic x, x, asr 31 because we can test if CC==LT && RHS==TrueVal==0 && LHS==FalseVal
Further, give a function x > 255 ? 255 : (x < 0 ? 0 :x), we should lower it to: usat x, #8
However, things become more complicated if we have
((x < 0 ? 0 :x) << n ) & mask ...
Because it will first be converted to
x < 0 ? 0 : ((x << n) & mask)
Now, it's hard to...
2016 Jul 27
0
Hitting assertion failure related to vectorization + instcombine
...t;>> '@strsave'
>>> >>>>
>>> >>>> ---
>>> >>>>
>>> >>>> Looking at the code, the issue is with this line:
>>> >>>>
>>> >>>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X),
>>> >>>> m_APInt(C)))
>>> >>>> &&
>>> >>>> *Y == ~*C)
>>> >>>>
>>> >>>> In this case Y is a 128-bit APInt, and so is the value that C is
>>> >&g...
2016 Jul 28
1
Hitting assertion failure related to vectorization + instcombine
...> >>> >>>>
> >>> >>>> ---
> >>> >>>>
> >>> >>>> Looking at the code, the issue is with this line:
> >>> >>>>
> >>> >>>> if (TrueVal == X && match(FalseVal, m_And(m_Specific(X),
> >>> >>>> m_APInt(C)))
> >>> >>>> &&
> >>> >>>> *Y == ~*C)
> >>> >>>>
> >>> >>>> In this case Y is a 128-bit APInt, and so is the value that...
2015 Jan 15
3
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
On Thu, Jan 15, 2015 at 1:26 PM, Nick Lewycky <nlewycky at google.com> wrote:
> On 15 January 2015 at 13:10, Daniel Berlin <dberlin at dberlin.org> wrote:
>
>> Yes.
>> I've attached an updated patch that does the following:
>>
>> 1. Fixes the partialalias of globals/arguments
>> 2. Enables partialalias for cases where nothing has been unified to
2015 Jan 15
2
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
...dgeType::Assign, AttrNone));
+ // Condition is irrelevant, it is evaluated, but not loaded,
+ // stored, or assigned
+ // The results of the select are assigned
auto *TrueVal = Inst.getTrueValue();
Output.push_back(Edge(&Inst, TrueVal, EdgeType::Assign, AttrNone));
auto *FalseVal = Inst.getFalseValue();
@@ -768,7 +772,10 @@ static Optional<StratifiedAttr> valueToAttrIndex(Value *Val) {
return AttrGlobalIndex;
if (auto *Arg = dyn_cast<Argument>(Val))
- if (!Arg->hasNoAliasAttr())
+ // Only pointer arguments should have the argument attribute,
+...
2015 Jan 14
3
[LLVMdev] question about enabling cfl-aa and collecting a57 numbers
Oh, sorry, i didn't rebase it when i changed the fix, you would have had to
apply the first on top of the second.
Here is one against HEAD
On Wed, Jan 14, 2015 at 12:32 PM, Ana Pazos <apazos at codeaurora.org> wrote:
> Daniel, your patch does not apply cleanly. Are you on the tip?
>
> The code I see there is no line if (QueryResult == MayAlias|| QueryResult == PartialAlias)
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more