search for: falcons

Displaying 20 results from an estimated 487 matches for "falcons".

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2016 Dec 06
0
[PATCH 3/8] core: add falcon library functions
...Ability for an engine to obtain and later release a given falcon, * Abstractions for basic operations (IMEM/DMEM access, start, etc) * Abstractions for secure operations if a falcon is secure Abstractions make it easy to e.g. start a falcon, without having to care about its details. For instance, falcons in secure mode need to be started by writing to a different register. Right now the abstractions variants only cover secure vs. non-secure falcon, but more will come as e.g. SEC2 support is added. This is still a WIP as other functions previously done by engine/falcon.c need to be reimplemented....
2009 May 12
2
add error check for ocfs2_read_locked_inode() call
After upgrading from 2.6.28.10 to 2.6.29.3 I've saw following new errors in kernel log: May 12 14:46:41 falcon-cl5 May 12 14:46:41 falcon-cl5 (6757,7):ocfs2_read_locked_inode:466 ERROR: status = -22 Only one node is mounted volumes in cluster: /dev/sde on /home/apache/users/D1 type ocfs2 (rw,_netdev,noatime,heartbeat=local) /dev/sdd on /home/apache/users/D2 type ocfs2
2016 Dec 06
9
[PATCH 0/8] Falcon library
...plicate falcon-related code into a single library, using the existing nvkm_falcon structure as a basis. Note that this currently makes struct nvkm_falcon used for two different purposes: this fact is acknowledged, and temporary. It just makes it easier to review this first step. Using the library, falcons are now acquired by a given subdev using nvkm_falcon_get(), and released with nvkm_falcon_put(). This allows different engines to share a falcon (as devinit, secboot and pmu will need to do), but forces us to think about falcon ownership and handling them to the next engine properly. A falcon'...
2016 Dec 13
15
[PATCH v2 0/15] Falcon library
...plicate falcon-related code into a single library, using the existing nvkm_falcon structure as a basis. Note that this currently makes struct nvkm_falcon used for two different purposes: this fact is acknowledged, and temporary. It just makes it easier to review this first step. Using the library, falcons are now acquired by a given subdev using nvkm_falcon_get(), and released with nvkm_falcon_put(). This allows different engines to share a falcon (as devinit, secboot and pmu will need to do), but forces us to think about falcon ownership and handling them to the next engine properly. Right now the...
2013 Dec 07
0
[PATCH] drm/nouveau/falcon: use vmalloc to create firwmare copies
Some firmware images may be large (64K), so using kmalloc memory is inappropriate for them. Use vmalloc instead, to avoid high-order allocation failures. Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Cc: stable at vger.kernel.org --- Couldn't get video decoding started on a long-running system due to high-order allocation failures. This seems like a fine use-case for vmalloc.
2017 Sep 13
2
Nouveau: kernel hang on Optimus+Intel+NVidia GeForce 1060m
Hi, the system fails to initialize your vbios using secureboot (i had a rare chance to on my system to witness it again), for now i traced it to acr_boot_falcon() in "linux/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c" where it throws -110 which is -ETIMEDOUT. You could try to increase the timeout and see if it helps something, similar to the following: diff --git
2014 Sep 26
3
NVIDIA Falcon Microprocessor Security
Hi, all. Below is a link to a brief document describing some changes in NVIDIA Falcon processors ("fuc", in Nouveau-speak, IIUC) that happened in Maxwell: certain aspects of the chip will only be available to Falcon firmware images signed by NVIDIA. So far, the set of restricted things is pretty small, but I expect this list will slowly grow over future hardware generations.
2017 Mar 29
15
[PATCH 00/15] Support for GP10B chipset
...SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot: let LS post_run hooks return error secboot: start LS firmware in post-run hook secboot/gm20b: specify MC base address as argument secboot: add GP10B support msgqueue: support for GP10B PMU firmware fifo: add GP10B support fb: ad...
2019 Oct 09
0
[PATCH] drm/nouveau/falcon: make unexported objects static
Make the msgqueue_0148cdec_acr_func and msgqueue_0148cdec_func static to avoid the following sparse warnings: drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c:230:1: warning: symbol 'msgqueue_0148cdec_acr_func' was not declared. Should it be static? drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0148cdec.c:241:1: warning: symbol 'msgqueue_0148cdec_func' was not declared.
2017 Feb 22
1
(DeviceIoControl, FSCTL_SET_SPARSE)
For some reason It's not erroring now, I will look into it more, but I suspect it鈥檚 the settings, the last thing mentioned David > [globa]l section is fine, as long as it's not also set in the share section. So, yeah, that may have fixed im for the time being not getting the sparse errors, for the first time in 4 months, however, there is a couple other problems, so hopefully they
2016 Dec 14
18
[PATCH v5 0/18] Secure Boot refactoring
Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA
2014 Sep 27
0
NVIDIA Falcon Microprocessor Security
...way, and we can support multiple paths if/when we need to. One immediate question I have is that given that FECS/GPCCS pretty much have zero permissions already outside of the NV_PGRAPH range, what restrictions are in place there that would prevent us from continuing to use our own ucode on these falcons? > > If NVIDIA just released firmware binaries along side each NVIDIA GPU driver > release, would it be reasonable for Nouveau to pick and choose which > firmware you'd like promoted to, e.g., > > http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/tre...
2004 Jan 04
1
XP can browse samba by IP, but not by name - NMB issues?
I have an XP home (falcon) and an XP pro (tatooine) machine, both behind a rh9 box (hoth) acting as firewall. I've been trying to get samba set up on the linux box. I think I have it mostly working except that the XP boxes won't list hoth under "My Network Places - Microsoft Windows Network - MSHOME", and I cannot access hoth by name at all from the XP-pro box (by IP, I can
2016 Jan 18
0
[PATCH v2 2/5] core: add support for secure boot
On GM20x and later GPUs, firmware for some essential falcons (notably FECS) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to access certain registers, in a process known as Secure Boot. Secure Boot requires the building of a binary blob containing the firmwares and signatures of the falcons to be loaded. Th...
2016 Oct 11
10
[PATCH 0/8] Secure Boot refactoring
Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send
2018 Dec 14
1
[PATCH] drm/nouveau/falcon: avoid touching registers if engine is off
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> --- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c b/drivers/gpu/drm/nouveau/nvkm/engine/falcon.c index 816ccaedfc73..8675613e142b 100644 ---
2019 Feb 09
0
[PATCH AUTOSEL 4.20 37/42] drm/nouveau/falcon: avoid touching registers if engine is off
From: Ilia Mirkin <imirkin at alum.mit.edu> [ Upstream commit a5176a4cb85bb6213daadf691097cf411da35df2 ] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Sasha Levin <sashal at kernel.org> --- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 7
2019 Feb 09
0
[PATCH AUTOSEL 4.19 26/28] drm/nouveau/falcon: avoid touching registers if engine is off
From: Ilia Mirkin <imirkin at alum.mit.edu> [ Upstream commit a5176a4cb85bb6213daadf691097cf411da35df2 ] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Sasha Levin <sashal at kernel.org> --- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 7
2019 Feb 09
0
[PATCH AUTOSEL 4.14 15/16] drm/nouveau/falcon: avoid touching registers if engine is off
From: Ilia Mirkin <imirkin at alum.mit.edu> [ Upstream commit a5176a4cb85bb6213daadf691097cf411da35df2 ] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108980 Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu> Signed-off-by: Ben Skeggs <bskeggs at redhat.com> Signed-off-by: Sasha Levin <sashal at kernel.org> --- drivers/gpu/drm/nouveau/nvkm/engine/falcon.c | 7
2016 Oct 27
15
[PATCH v2 00/14] Secure Boot refactoring
This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the