search for: falcon_id

...code_img *); - /** * ls_ucode_img_load() - create a lsf_ucode_img and load it */ -static struct ls_ucode_img * -ls_ucode_img_load(const struct nvkm_subdev *subdev, lsf_load_func load_func) +struct ls_ucode_img * +acr_r352_ls_ucode_img_load(const struct acr_r352 *acr, + enum nvkm_falconidx falcon_id) { - struct ls_ucode_img *img; + const struct nvkm_subdev *subdev = acr->base.subdev; + struct ls_ucode_img_r352 *img; int ret; img = kzalloc(sizeof(*img), GFP_KERNEL); if (!img) return ERR_PTR(-ENOMEM); - ret = load_func(subdev, img); + img->base.falcon_id = falcon_id; + + ret...

.../** - * struct lsf_ucode_desc - LS falcon signatures - * @prd_keys: signature to use when the GPU is in production mode - * @dgb_keys: signature to use when the GPU is in debug mode - * @b_prd_present: whether the production key is present - * @b_dgb_present: whether the debug key is present - * @falcon_id: ID of the falcon the ucode applies to - * - * Directly loaded from a signature file. - */ -struct lsf_ucode_desc { - u8 prd_keys[2][16]; - u8 dbg_keys[2][16]; - u32 b_prd_present; - u32 b_dbg_present; - u32 falcon_id; -}; - -/** - * struct lsf_lsb_header - LS firmware header - * @signature: si...

...f0..cdba9ffc5bbe 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -214,12 +214,6 @@ ls_ucode_img_fill_headers(struct acr_r352 *acr, struct ls_ucode_img *img, const struct acr_r352_ls_func *func = acr->func->ls_func[img->falcon_id]; - if (img->ucode_header) { - nvkm_fatal(acr->base.subdev, - "images withough loader are not supported yet!\n"); - return offset; - } - /* Fill WPR header */ whdr->falcon_id = img->falcon_id; whdr->bootstrap_owner = acr->base.func->boot_falcon; @@ -309...

...52 *acr, struct list_head *imgs, { struct ls_ucode_img *_img; u32 pos = 0; + u32 max_desc_size = 0; + u8 *gdesc; + + /* Figure out how large we need gdesc to be. */ + list_for_each_entry(_img, imgs, node) { + const struct acr_r352_ls_func *ls_func = + acr->func->ls_func[_img->falcon_id]; + + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); + } + + gdesc = kmalloc(max_desc_size, GFP_KERNEL); + if (!gdesc) + return -ENOMEM; nvkm_kmap(wpr_blob); @@ -421,7 +435,6 @@ acr_r352_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs, struct ls_ucode_img_r352 *i...

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

...size = 0; > + u8 *gdesc; > + > + /* Figure out how large we need gdesc to be. */ > + list_for_each_entry(_img, imgs, node) { > + const struct acr_r352_ls_func *ls_func = > + acr->func->ls_func[_img->falcon_id]; > + > + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); > + } > + > + gdesc = kmalloc(max_desc_size, GFP_KERNEL); > + if (!gdesc) > + return -ENOMEM; > > nvkm_kmap(wpr_blob); > > @@ -421,7 +435,6...

Hi everyone, Apologies for the big patchset. This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send

.../** + * struct lsf_ucode_desc - LS falcon signatures + * @prd_keys: signature to use when the GPU is in production mode + * @dgb_keys: signature to use when the GPU is in debug mode + * @b_prd_present: whether the production key is present + * @b_dgb_present: whether the debug key is present + * @falcon_id: ID of the falcon the ucode applies to + * + * Directly loaded from a signature file. + */ +struct lsf_ucode_desc { + u8 prd_keys[2][16]; + u8 dbg_keys[2][16]; + u32 b_prd_present; + u32 b_dbg_present; + u32 falcon_id; +}; + +/** + * struct lsf_lsb_header - LS firmware header + * @signature: si...

...u8 *gdesc; >> + >> + /* Figure out how large we need gdesc to be. */ >> + list_for_each_entry(_img, imgs, node) { >> + const struct acr_r352_ls_func *ls_func = >> + acr->func->ls_func[_img->falcon_id]; >> + >> + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); >> + } >> + >> + gdesc = kmalloc(max_desc_size, GFP_KERNEL); >> + if (!gdesc) >> + return -ENOMEM; >> >> nvkm_kmap(wp...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

...54,7 +323,7 @@ ls_ucode_mgr_write_wpr(struct acr_r352 *acr, struct ls_ucode_mgr *mgr, nvkm_kmap(wpr_blob); - list_for_each_entry(img, &mgr->img_list, node) { + list_for_each_entry(img, imgs, node) { const struct acr_r352_ls_func *ls_func = acr->func->ls_func[img->falcon_id]; u8 gdesc[ls_func->bl_desc_size]; @@ -400,11 +369,14 @@ acr_r352_prepare_ls_blob(struct acr_r352 *acr, u64 wpr_addr, u32 wpr_size, unsigned long managed_falcons) { const struct nvkm_subdev *subdev = acr->base.subdev; - struct ls_ucode_mgr mgr; + struct list_head imgs; + struct ls_...

This is a highly changed revision of the first patch series that adds secure boot support to Nouveau. This code still depends on NVIDIA releasing official firmware files, but the files released with SHIELD TV and Pixel C can already be used on a Jetson TX1. As you know we are working hard to release the official firmware files, however in the meantime it doesn't hurt to review the code so it

...km/subdev/pmu/gm20b.c @@ -52,8 +52,13 @@ gm20b_pmu_acr_bootstrap_falcon(struct nvkm_falcon *falcon, ret = nvkm_falcon_cmdq_send(pmu->hpq, &cmd.cmd.hdr, gm20b_pmu_acr_bootstrap_falcon_cb, &pmu->subdev, msecs_to_jiffies(1000)); - if (ret >= 0 && ret != cmd.falcon_id) - ret = -EIO; + if (ret >= 0) { + if (ret != cmd.falcon_id) + ret = -EIO; + else + ret = 0; + } + return ret; } diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.c index 39c86bc56310..5b81c7320479 100644 --- a/drivers/gpu/dr...

...t;> + >>> + /* Figure out how large we need gdesc to be. */ >>> + list_for_each_entry(_img, imgs, node) { >>> + const struct acr_r352_ls_func *ls_func = >>> + acr->func->ls_func[_img->falcon_id]; >>> + >>> + max_desc_size = max(max_desc_size, ls_func->bl_desc_size); >>> + } >>> + >>> + gdesc = kmalloc(max_desc_size, GFP_KERNEL); >>> + if (!gdesc) >>> + return -ENOMEM; >>&g...

New version of the secure boot code that works with the blobs just merged into linux-firmware. Since the required Mesa patches are also merged, this set is the last piece of the puzzle to get out-of-the-box accelerated Maxwell 2. The basic code remains the same, with a few improvements with respect to how secure falcons are started. Hopefully the patchset is better split too. I have a

...c0273158f6..c2ae525a0780 100644 --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c @@ -279,6 +279,7 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)                 u32 flags;                 u32 falcon_id;         } cmd; +       const struct nvkm_subdev *subdev = priv->falcon->owner;           memset(&cmd, 0, sizeof(cmd));   @@ -290,7 +291,8 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum nvkm_secboot_falcon falcon)         nvkm_msgqueue_post(priv, MSGQUEUE_MSG_PRIORITY_HIGH, &cmd....

...4 > --- a/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c > +++ b/drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c > @@ -279,6 +279,7 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum > nvkm_secboot_falcon falcon) > u32 flags; > u32 falcon_id; > } cmd; > + const struct nvkm_subdev *subdev = priv->falcon->owner; > > memset(&cmd, 0, sizeof(cmd)); > > @@ -290,7 +291,8 @@ acr_boot_falcon(struct nvkm_msgqueue *priv, enum > nvkm_secboot_falcon falcon) > nvkm_msgqueue_post(priv, M...