Displaying 3 results from an estimated 3 matches for "fail_if".
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fail_id
2013 Aug 28
3
[PATCH] x86: AVX instruction emulation fixes
...}
}
- vex.reg ^= 0xf;
- if ( !mode_64bit() )
- vex.reg &= 0x7;
- else if ( !vex.r )
+ if ( mode_64bit() && !vex.r )
rex_prefix |= REX_R;
fail_if(vex.opcx != vex_0f);
@@ -3899,8 +3896,9 @@ x86_emulate(
else
{
fail_if((vex.opcx != vex_0f) ||
- (vex.reg && ((ea.type == OP_MEM) ||
- !(vex.pfx & VEX_PREFIX_SCALAR_MASK))));
+ ((vex.reg...
2011 Nov 30
0
[PATCH 2/4] x86/emulator: add emulation of SIMD FP moves
...t) = sse_prefix[(vex_pfx) - 1]; \
+} while (0)
+
union vex {
uint8_t raw[2];
struct {
@@ -3850,6 +3860,76 @@ x86_emulate(
case 0x19 ... 0x1f: /* nop (amd-defined) */
break;
+ case 0x2b: /* {,v}movntp{s,d} xmm,m128 */
+ /* vmovntp{s,d} ymm,m256 */
+ fail_if(ea.type != OP_MEM);
+ /* fall through */
+ case 0x28: /* {,v}movap{s,d} xmm/m128,xmm */
+ /* vmovap{s,d} ymm/m256,ymm */
+ case 0x29: /* {,v}movap{s,d} xmm,xmm/m128 */
+ /* vmovap{s,d} ymm,ymm/m256 */
+ fail_if(vex.pfx & VEX_PREFIX_SCALAR_MASK);
+...
2011 Dec 15
10
fsincos emulation on AMD CPUs
All,
in the light of erratum #573 I''m wondering if we need to tweak or
conditionally suppress fsincos emulation. The question is whether there
is any possibility for getting the emulator to hit this instruction on AMD
(as no real mode emulation ought to be taking place there), i.e.
whether there are places where emulation gets continued eagerly
in anticipation of the need for emulation