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2013 Jan 23
0
[LLVMdev] Instruction Constraints Question
...?
In this case, $src1 is also the destination register. A masked gather will
merge the conditionally selected elements into the input vector.
-Cameron
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2013 Jan 23
3
[LLVMdev] Instruction Constraints Question
>> It doesn't look like TableGen supports Constraints beyond EARLY_CLOBBER
>> and TIED_TO. We would need to add a constraint such as "$dst != $src1,
>> $dst != $mask, $src1 != $mask" to the current patterns to enforce the
>> rules.
> You can emulate such constraints via early clobbing. Just mark dst as
> early clobbing.
How would that (or any early