Displaying 2 results from an estimated 2 matches for "f9feb3ea".
2011 Dec 08
0
[LLVMdev] Register allocation in two passes
On Dec 8, 2011, at 12:15 PM, Borja Ferrer wrote:
> Jakob I've just noticed that I'm getting false positives about spills when there are actually none.
> What is happening is that although execution reaches to the line spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the spill is avoided because the register gets rematted. This is the debug output I'm
2011 Dec 08
2
[LLVMdev] Register allocation in two passes
Jakob I've just noticed that I'm getting false positives about spills when
there are actually none.
What is happening is that although execution reaches to the line
spiller().spill(LRE); inside RAGreedy::selectOrSplit() the insertion of the
spill is avoided because the register gets rematted. This is the debug
output I'm getting to show what I mean:
Inline spilling