Displaying 3 results from an estimated 3 matches for "f9ef1c08".
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f9e1508
2010 Sep 04
1
[LLVMdev] Possible missed optimization?
Indeed, i've marked it as commutable:
let isCommutable = 1,
isTwoAddress = 1 in
def XORRdRr : FRdRr<0b0010,
0b01,
(outs GPR8:$dst),
(ins GPR8:$src1, GPR8:$src2),
"xor\t$dst, $src2",
[(set GPR8:$dst, (xor GPR8:$src1, GPR8:$src2))]>;
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An HTML
2010 Sep 04
0
[LLVMdev] Possible missed optimization?
I've noticed this pattern happening with other operators aswell, but used
xor in this example. As i said before, i tried with different register
allocation orders, but it will produce always the same result. GCC is
emitting longer code, but since LLVM is so nearer to the optimal code
sequence i wanted to reach it.
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2010 Sep 04
3
[LLVMdev] Possible missed optimization?
...utput of -debug-only=regcoalescing to see what is going wrong.
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