search for: f8rc

...instruction set, each of the existing floating-point registers becomes the first of two vector elements. I am having trouble optimizing the BUILD_VECTOR operation for the case where I am building a v2f64 vector out of two operands. I tried writing this pattern as: def : Pat<(v2f64 (build_vector F8RC:$A, F8RC:$B)), (FSMFP (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), F8RC:$A, sub_64), (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), F8RC:$B, sub_64))>; Where the FSMFP instruction copies the first vector element of the second operand to the second vector element of the first operan...

...gt; Index: lib/Target/PowerPC/PPCInstrInfo.td > =================================================================== > --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) > +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) > @@ -773,6 +773,10 @@ > [(store F8RC:$frS, xaddr:$dst)]>; > } > > +let isBarrier = 1 in > +def SYNC : XForm_24_sync<31, 598, (outs), (ins), > + "sync", LdStSync, > + [(int_ppc_sync)]>; > > //===-----------------------------------------------...

..., [IntrWriteMem]>; } Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -773,6 +773,10 @@ [(store F8RC:$frS, xaddr:$dst)]>; } +let isBarrier = 1 in +def SYNC : XForm_24<31, 598, (outs), (ins), + "sync", LdStSync, + [(int_ppc_sync)]>; //===----------------------------------------------------------------------===// // PPC32 Arithmetic Ins...

..., [IntrWriteMem]>; } Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -773,6 +773,10 @@ [(store F8RC:$frS, xaddr:$dst)]>; } +let isBarrier = 1 in +def SYNC : XForm_24_sync<31, 598, (outs), (ins), + "sync", LdStSync, + [(int_ppc_sync)]>; //===----------------------------------------------------------------------===// // PPC32 A...

...et/PowerPC/PPCInstrInfo.td >> =================================================================== >> --- lib/Target/PowerPC/PPCInstrInfo.td (revision 54985) >> +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) >> @@ -773,6 +773,10 @@ >> [(store F8RC:$frS, xaddr:$dst)]>; >> } >> >> +let isBarrier = 1 in >> +def SYNC : XForm_24_sync<31, 598, (outs), (ins), >> + "sync", LdStSync, >> + [(int_ppc_sync)]>; >> >> // >> = >> =...

On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: > Hi all, > > I'm trying to implement llvm.memory.barrier on PowerPC. I've modelled > my patch (attached) on the implementation in X86, but when I try and > compile my test file (also attached) with llc I get the error "Cannot > yet select: 0x10fa4ad0: ch = MemBarrier 0x10fa4828, 0x10fa4c68, > 0x10fa4be0,

This looks OK to check in, do you have write access? On Aug 21, 2008, at 6:38 AMPDT, Gary Benson wrote: > Dale Johannesen wrote: >> On Aug 19, 2008, at 7:18 AMPDT, Gary Benson wrote: >>> I'm trying to implement llvm.memory.barrier on PowerPC. I've >>> modelled my patch (attached) on the implementation in X86, but >>> when I try and compile my test

...-------- next part -------------- Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.h (working copy) @@ -152,6 +152,11 @@ /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. MTFSF, + /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These + /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap + /// and llvm.atomic.swap intrinsics. + ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...-------- next part -------------- Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h (revision 53464) +++ lib/Target/PowerPC/PPCISelLowering.h (working copy) @@ -152,6 +152,11 @@ /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. MTFSF, + /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These + /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap + /// and llvm.atomic.swap intrinsics. + ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...-------- next part -------------- Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.h (working copy) @@ -152,6 +152,11 @@ /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. MTFSF, + /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These + /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap + /// and llvm.atomic.swap intrinsics. + ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...-------- next part -------------- Index: lib/Target/PowerPC/PPCISelLowering.h =================================================================== --- lib/Target/PowerPC/PPCISelLowering.h (revision 52957) +++ lib/Target/PowerPC/PPCISelLowering.h (working copy) @@ -152,6 +152,11 @@ /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR. MTFSF, + /// ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP - These + /// correspond to the llvm.atomic.load.add, llvm.atomic.cmp.swap + /// and llvm.atomic.swap intrinsics. + ATOMIC_LOAD_ADD, ATOMIC_CMP_SWAP, ATOMIC_SWAP...