search for: f51cedce

Displaying 2 results from an estimated 2 matches for "f51cedce".

[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
2020 Oct 29
0
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
...; https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev -- Sam Elliott Software Team Lead Senior Software Developer - LLVM and OpenTitan lowRISC CIC -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20201029/f51cedce/attachment.html>
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
2020 Sep 29
2
[riscv] How do I use the RISC-V Vector extension instructions in LLVM IR?
Hi Everyone, I am wondering how to use RISC-V V (Vector) extension instructions in LLVM IR. In 2019 Kruppe and Espasa gave a talk [1] overviewing the Vector extension and on slide 16 [2] they show LLVM IR samples which use the vector instructions through intrinsic functions, such as: %vl = call i32 @llvm.riscv.vsetvl(i32 %n) At the time of the talk (April 2019) LLVM support for the V