Displaying 3 results from an estimated 3 matches for "f4778f08a038".
2020 Feb 13
1
[PATCH 1/4] drm/nouveau/kms/nv50-: Probe SOR caps for DP interlacing support
.../gm200: fork from gf100")
e69dae85c90b ("drm/nouveau/bar/nv50,g84: drop mmu invalidate")
e75182f68b7b ("drm/nouveau/kms/nv50: use "low res" lut for indexed mode")
eaf1a69110f4 ("drm/nouveau/mmu: add base for type-based memory allocation")
f4778f08a038 ("drm/nouveau/kms/nv50: fix handling of gamma since atomic conversion")
f5650478ab07 ("drm/nouveau/disp/nv50-: pass nvkm_memory objects for channel push buffers")
v4.9.213: Failed to apply! Possible dependencies:
11fc017dfb1e ("drm/nouveau/kms/nv50: prepare for dou...
2019 Sep 13
6
[PATCH 1/4] drm/nouveau: dispnv50: Don't create MSTMs for eDP connectors
On the ThinkPad P71, we have one eDP connector exposed along with 5 DP
connectors, resulting in a total of 11 TMDS encoders. Since the GPU on
this system is also capable of MST, we create an additional 4 fake MST
encoders for each DP port. Unfortunately, we also do this for the eDP
port as well, resulting in:
1 eDP port: +1 TMDS encoder
+4 DPMST encoders
5 DP ports: +2 TMDS
2020 Feb 12
8
[PATCH 0/4] drm/nouveau: DP interlace fixes
Currently, nouveau doesn't actually bother to try probing whether or not
it can actually handle interlaced modes over DisplayPort. As a result,
on volta and later we'll end up trying to set an interlaced mode even
when it's not supported and cause the front end for the display engine
to hang.
So, let's teach nouveau to reject interlaced modes on hardware that
can't actually