search for: f3_12

...gen: http://llvm.org/docs/TableGenFundamentals.html#multiclass Basically this lets you use one definition to implement multiple different instructions. For example, most instructions in the sparc target come in "reg,reg" and "reg,imm" forms. As such, it defines: multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { def rr : F3_1<2, Op3Val, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;...

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

...ulticlass This is very interesting. > Basically this lets you use one definition to implement multiple different > instructions. For example, most instructions in the sparc target come in > "reg,reg" and "reg,imm" forms. As such, it defines: > > multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { > def rr : F3_1<2, Op3Val, > (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c), > !strconcat(OpcStr, " $b, $c, $dst"), > [(set IntRegs:$dst, (OpNode IntRegs:$b, In...

...;> .... >> The GlobalAddress for variable c is replaced by an ADD(HI(c), LO >> (c)) during lowering. I assume the code-generator cant place values >> in the address registers? All address-registers are elements in the >> register sets IntRegs and AddrRegs. > > /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. > multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { > .... > } > > defm ADD : F3_12<"add", 0b000000, add>; > > Instruction ADD output register class is IntRegs. It does not...

...d RegClass size = 4, align = 4 > > The GlobalAddress for variable c is replaced by an ADD(HI(c), LO > (c)) during lowering. I assume the code-generator cant place values > in the address registers? All address-registers are elements in the > register sets IntRegs and AddrRegs. /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot. multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> { def rr : F3_1<2, Op3Val, (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c), !strconcat(OpcStr, " $b, $c, $dst&quot...

Hi! I'm writing a new back-end for a new architecture. First, I'll do some "tests" with an existing back-end (I chose the Sparc back-end). My architecture has special address-registers and I want to add such new address-registers to my Sparc back-end. 1) I defined a new register call AddrRegs 2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. )) 3) I

...uple of questions. I am using LLVM 2.6. First, if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, defm SRA : F3_12<"mysra", 0b100111, sra>; Is this correct? When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes "mysra". However, whe...

...LVM 2.6. > > First, > if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right? > Using Sparc as an example, if I wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would write, > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > Is this correct? Yes. > When I run llc with option -march=sparc, after I make the modification, it still outputs "sra", not "mysra". I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes "my...

...f I want to change the name of an instruction, all I need to do is to > > modify the XXXInstrInfo.td, right? Using Sparc as an example, if I > > wanted to output "mysra" instead of "sra", in SparcInstrInfo.td, I would > > write, > > > > defm SRA : F3_12<"mysra", 0b100111, sra>; > > > > Is this correct? > > Yes. IMHO, this is a poor way to do this kind of thing. It eventually leads to confusion where someone things SRA means "sra" and someone else thinks it meas "mysra." It gets worse as &quo...