Displaying 2 results from an estimated 2 matches for "f32node".
2011 Nov 03
3
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...imm_imm,
ADD_reg_reg, ADD_imm_reg, ADD_reg_imm).
I have tried a few different ways to make this work in tablegen, but I
have been unsuccessful so far. Here is an example of something I have
tried. It fails to compile with tablegen, but I hope it can help
demonstrate what I am trying to do:
def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>;
def F32Op : Operand <f32> {
let MIOperandInfo = (ops GPR, f32imm);
}
def ADD : InstAMD <
(outs GPR:$dst),
(ins F32Op:$src0, F32Op:$src1),
"ADD $dst, $src0, $src1"),
[(set GP...
2011 Nov 03
0
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
...eg_imm).
>
> I have tried a few different ways to make this work in tablegen, but I
> have been unsuccessful so far. Here is an example of something I have
> tried. It fails to compile with tablegen, but I hope it can help
> demonstrate what I am trying to do:
>
>
> def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>;
>
> def F32Op : Operand <f32> {
> let MIOperandInfo = (ops GPR, f32imm);
> }
>
> def ADD : InstAMD <
> (outs GPR:$dst),
> (ins F32Op:$src0, F32Op:$src1),
> "ADD...