Displaying 18 results from an estimated 18 matches for "exttyp".
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2004 Aug 06
4
Ices 2.0 beta3
This is to announce the release of ices 2.0 beta 3. The source client
for streaming Ogg Vorbis to Icecast 2.
After far too much time having passed since beta 2, where many fixes and
updates have been applied, it's time to push for a full 2.0 release.
This beta is really to flush out any remaining issues, so no new
functionality is to be added until after the 2.0 release.
Download from
2004 Aug 06
4
Ices 2.0 beta3
This is to announce the release of ices 2.0 beta 3. The source client
for streaming Ogg Vorbis to Icecast 2.
After far too much time having passed since beta 2, where many fixes and
updates have been applied, it's time to push for a full 2.0 release.
This beta is really to flush out any remaining issues, so no new
functionality is to be added until after the 2.0 release.
Download from
2010 Jul 17
2
[LLVMdev] v16i32/v16f32
I tried adding them in my backend however I run into the assertion
assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
ExtType < array_lengthof(LoadExtActions) &&
"Table isn't big enough!");
What does the assertion mean ?
thanks for all help!!
shrey
On Wed, Jul 14, 2010 at 6:56 PM, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Wed, Jul 14, 2010 at 6:48 PM, shreyas kr...
2013 Mar 04
1
[LLVMdev] Custom Lowering of ARM zero-extending loads
...o accomplish that:
1. Register the ZEXTLOAD for custom lowering:
setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Custom);
2. Implement a custom lowering function:
static SDValue LowerExtLoad(SDValue Op, SelectionDAG &DAG) {
LoadSDNode *LD = dyn_cast<LoadSDNode>(Op.getNode());
ISD::LoadExtType ExtType = LD->getExtensionType();
if (LD->getExtensionType() == ISD::ZEXTLOAD) {
DEBUG(errs() << "ZEXTLOAD\n");
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
DebugLoc dl = Op.getNode()->getDebugLoc();
SDValue LdResult = DAG.ge...
2010 Jul 17
0
[LLVMdev] v16i32/v16f32
On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> I tried adding them in my backend however I run into the assertion
>
> assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
> ExtType < array_lengthof(LoadExtActions) &&
> "Table isn't big enough!");
>
> What does the assertion mean ?
That means you forgot to bump up LAST_VALUETYPE.
-Eli
2015 Mar 03
3
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
I'm curious about this code in ReduceLoadWidth (and in DAGCombiner in
general):
if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
return SDValue
<http://llvm.org/docs/doxygen/html/classllvm_1_1SDValue.html>();
LegalOperations is false for the first pre-legalize pass and true for the
post-legalize pass. The first pass is target-independent yes? So that makes
sense.
The issue we are having is this: we don...
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...ZEXTLOAD i16. I'm wondering if there is:
>
> a) A way to turn off this optimization in DAGCombine if your target
> doesn't support LD2 natively
This.
I think you're talking about DAGCombiner::ReduceLoadWidth... and the
"if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))" is
supposed to ensure that the transformation in question is safe. That
said, IIRC I fixed a bug there recently; are you using trunk?
-Eli
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
...there is:
>>
>> a) A way to turn off this optimization in DAGCombine if your target
>> doesn't support LD2 natively
>
> This.
>
> I think you're talking about DAGCombiner::ReduceLoadWidth... and the
> "if (LegalOperations&& !TLI.isLoadExtLegal(ExtType, ExtVT))" is
> supposed to ensure that the transformation in question is safe. That
> said, IIRC I fixed a bug there recently; are you using trunk?
Perfect! I'm using 2.8 for now (am hoping to roll forward to trunk and
stay there in a month or two), and 2.8 only had that check f...
2011 Jul 27
2
[LLVMdev] Avoiding load narrowing in DAGCombiner
Hi All,
I'm writing a backend for a target which only supports 4-byte,
4-byte-aligned loads and stores. I custom-lower all {*EXT}LOAD and
STORE nodes in TargetISelLowering.cpp to take advantage of all alignment
information available to the backend, rather than treat each load and
store conservatively, which takes O(10) instructions. My target's
allowsUnalignedMemoryOperations()
2011 Jul 27
0
[LLVMdev] Avoiding load narrowing in DAGCombiner
...> a) A way to turn off this optimization in DAGCombine if your target
>>> doesn't support LD2 natively
>>
>> This.
>>
>> I think you're talking about DAGCombiner::ReduceLoadWidth... and the
>> "if (LegalOperations&& !TLI.isLoadExtLegal(ExtType, ExtVT))" is
>> supposed to ensure that the transformation in question is safe. That
>> said, IIRC I fixed a bug there recently; are you using trunk?
>
> Perfect! I'm using 2.8 for now (am hoping to roll forward to trunk and stay
> there in a month or two), and 2.8...
2015 Mar 03
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
...med.bougacha at gmail.com>
wrote:
> On Tue, Mar 3, 2015 at 10:35 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
> > I'm curious about this code in ReduceLoadWidth (and in DAGCombiner in
> > general):
> >
> > if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
> > return SDValue();
> >
> > LegalOperations is false for the first pre-legalize pass and true for the
> > post-legalize pass. The first pass is target-independent yes? So that
> makes
> > sense.
> >
> > The issue we are having is this: we...
2010 Jul 15
2
[LLVMdev] v16i32/v16f32
Hi
I find types such as v16i32, v16f32 missing in my llvm version 2.7
So does the following page not list them
http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html
is that intentional for any reason or can I just add them ?
thanks
shrey
2010 Jul 15
0
[LLVMdev] v16i32/v16f32
On Wed, Jul 14, 2010 at 6:48 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
> Hi
> I find types such as v16i32, v16f32 missing in my llvm version 2.7
>
> So does the following page not list them
> http://llvm.org/docs/doxygen/html/classllvm_1_1MVT.html
>
> is that intentional for any reason or can I just add them ?
As far as I know, they're not there
2010 Jul 17
1
[LLVMdev] v16i32/v16f32
...mail.com> wrote:
> On Fri, Jul 16, 2010 at 5:14 PM, shreyas krishnan <shreyas76 at gmail.com> wrote:
>> I tried adding them in my backend however I run into the assertion
>>
>> assert((unsigned)VT.SimpleTy < sizeof(LoadExtActions[0])*4 &&
>> ExtType < array_lengthof(LoadExtActions) &&
>> "Table isn't big enough!");
>>
>> What does the assertion mean ?
>
> That means you forgot to bump up LAST_VALUETYPE.
>
> -Eli
>
2009 May 21
0
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote:
> Can you explain why you chose the approach of using a new pass?
> I pictured removing LegalizeDAG's type legalization code would
> mostly consist of finding all the places that use TLI.getTypeAction
> and just deleting code for handling its Expand and Promote. Are you
> anticipating something more
2009 May 20
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
On May 20, 2009, at 1:34 PM, Eli Friedman wrote:
> On Wed, May 20, 2009 at 1:19 PM, Eli Friedman
> <eli.friedman at gmail.com> wrote:
>
>> Per subject, this patch adding an additional pass to handle vector
>>
>> operations; the idea is that this allows removing the code from
>>
>> LegalizeDAG that handles illegal types, which should be a significant
2009 May 21
2
[LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
...ult = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Tmp3, VAList, NULL, 0, VT);
- }
- // Remember that we legalized the chain.
- AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
- break;
-
- case ISD::LOAD: {
- LoadSDNode *LD = cast<LoadSDNode>(Node);
- ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(Node)
- ? ISD::EXTLOAD : LD->getExtensionType();
- Result = DAG.getExtLoad(ExtType, dl, NVT,
- LD->getChain(), LD->getBasePtr(),
- LD->getSrcValue(), LD->getSrcValueOffset(),
-...
2015 Mar 04
2
[LLVMdev] ReduceLoadWidth, DAGCombiner and non 8bit loads/extloads question.
...; On Tue, Mar 3, 2015 at 10:35 AM, Ryan Taylor <ryta1203 at gmail.com>
> wrote:
> >> > I'm curious about this code in ReduceLoadWidth (and in DAGCombiner in
> >> > general):
> >> >
> >> > if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT))
> >> > return SDValue();
> >> >
> >> > LegalOperations is false for the first pre-legalize pass and true for
> >> > the
> >> > post-legalize pass. The first pass is target-independent yes? So that
> >> > makes
>...