Displaying 4 results from an estimated 4 matches for "extracod".
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extraced
2018 Feb 07
2
retpoline mitigation and 6.0
...*MI, unsigned OpNo,
case 'w': // Print HImode register
case 'k': // Print SImode register
case 'q': // Print DImode register
+ case 'V': // Print native register without '%'
if (MO.isReg())
return printAsmMRegister(*this, MO, ExtraCode[0], O);
printOperand(*this, MI, OpNo, O);
--
dwmw2
2018 Feb 07
0
retpoline mitigation and 6.0
...case 'w': // Print HImode register
> case 'k': // Print SImode register
> case 'q': // Print DImode register
> + case 'V': // Print native register without '%'
> if (MO.isReg())
> return printAsmMRegister(*this, MO, ExtraCode[0], O);
> printOperand(*this, MI, OpNo, O);
>
> --
> dwmw2
>
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2018 Feb 07
0
retpoline mitigation and 6.0
On Wed, 2018-02-07 at 13:16 -0800, Guenter Roeck wrote:
> Here are my exact versions:
> llvm: 3afd566557f3 ("AMDGPU: Add 32-bit constant address space")
> clang: 848874aed95a ("[clang-format] Fix ObjC message arguments formatting.")
OK, mine are slightly newer than that now, but I now get a working 64-
bit defconfig build. It'll still break with any PV
2018 Feb 07
3
retpoline mitigation and 6.0
On Wed, Feb 07, 2018 at 08:44:32PM +0000, David Woodhouse wrote:
> On Wed, 2018-02-07 at 10:11 -0800, Guenter Roeck wrote:
>
> > On Wed, Feb 07, 2018 at 10:49:25AM +0000, David Woodhouse wrote:
> > > Hm, please could we also have the %V asm constraint modifier? That
> > > allows us to emit calls to the thunks from inline asm using the
> > > register that the