Displaying 1 result from an estimated 1 matches for "extendhalfwordword".
2011 Jan 29
3
[LLVMdev] Possible CellSPU Bug?
...t looks as if src and dest types have been swapped:
class XSHWVecInst<ValueType in_vectype, ValueType out_vectype>:
XSHWInst<(outs VECREG:$rDest), (ins VECREG:$rSrc),
[(set (out_vectype VECREG:$rDest),
(sext (in_vectype VECREG:$rSrc)))]>;
multiclass ExtendHalfwordWord {
def v4i32: XSHWVecInst<v4i32, v8i16>;
The multiclass name leads me to believe this was supposed to sign extend
from i16 to i32 but the XSHWVecInst class takes the types in SRC -> DST
order, not DST <- SRC order.
Is this pattern as intended, or did I find a real problem?...