Displaying 3 results from an estimated 3 matches for "experem".
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experim
2004 Jun 07
1
[LLVMdev] Some backend questions
...cessor, but has some snazzy addressing modes
> with pre/post in/decrements.
Yes. It's my impression that most DSPs have such "snazzy" addressing modes ;-)
> I assume that you're planning on only
> targetting the RISC core and not the vector copro?
Right. It would be experemely hard to generate efficient code for the vector
unit.
- Volodya
2004 Jun 07
0
[LLVMdev] Some backend questions
On Mon, 7 Jun 2004, Vladimir Prus wrote:
> > If you do this (which I recommend for the first step), you'll notice that
> > it produces pretty horrible code, as all immediates are copied into
> > registers before they are used. In other words, instead of getting:
> >
> > R2 = add R1, 17
> >
> > You'll get:
> >
> > R3 = mov 17
>
2004 Jun 07
2
[LLVMdev] Some backend questions
Chris Lattner wrote:
> > 1. The MachineInstrBuilder has methods to add register operand and
> > immediate operand. However, what would be really nice is a method to add
> > Value*. So, I would write:
> >
> > BuildMI(*BB, NM::add, 1).add(I.getOperand(0), I.getOperand(1));
> >
> > and depending on whether the passed Value* is contant or instruction,