Displaying 4 results from an estimated 4 matches for "expandstore".
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2016 Jun 28
0
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
Can someone comment below question whether it is wrong or not please?
2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
> Hi All,
>
> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>
> Let's see a example.
>
> * LLVM IR
> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>
> * SelectionDAG before vector legalization
> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
>
> * SelectionDAG aft...
2016 Jun 25
2
Question about VectorLegalizer::ExpandStore() with v4i1
Hi All,
I have a problem with VectorLegalizer::ExpandStore() with v4i1.
Let's see a example.
* LLVM IR
store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
* SelectionDAG before vector legalization
ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:i64
* SelectionDAG after vector legalization
ch = store<ST1[%16](...
2016 Jun 29
0
Question about VectorLegalizer::ExpandStore() with v4i1
...-------------------
Message: 8
Date: Tue, 28 Jun 2016 10:57:09 -0700 (PDT)
From: Rob Cameron via llvm-dev <llvm-dev at lists.llvm.org>
To: Ahmed Bougacha <ahmed.bougacha at gmail.com>
Cc: llvm-dev <llvm-dev at lists.llvm.org>
Subject: Re: [llvm-dev] Question about VectorLegalizer::ExpandStore()
with v4i1
Message-ID: <1150997581.449524.1467136629022.JavaMail.zimbra at sfu.ca>
Content-Type: text/plain; charset=utf-8
Hi, Ahmed.
A packed representation, one bit per i1, is natural and best for our
work, for sure. In the Parabix project, we produced very fast text
and byte stream p...
2016 Jun 28
2
Question about VectorLegalizer::ExpandStore() with v4i1
...ia llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Hi All,
>
> Can someone comment below question whether it is wrong or not please?
>
> 2016-06-25 7:52 GMT+01:00 jingu kang <jaykang10 at gmail.com>:
>> Hi All,
>>
>> I have a problem with VectorLegalizer::ExpandStore() with v4i1.
>>
>> Let's see a example.
>>
>> * LLVM IR
>> store <4 x i1> %edgeMask_for.body1314, <4 x i1>* %27
>>
>> * SelectionDAG before vector legalization
>> ch = store<ST1[%16](align=4), trunc to v4i1> t0, t128, t32, undef:...