search for: expandpostra

Hello everyone, I am running into an obscure issue with ExpandPostRA. Does anyone recognizes the following: The pass replaces a real copy with a "transfer" instruction: ********** EXPANDING POST-RA PSEUDO INSTRS ********** ********** Function: main real copy: %R15<def> = COPY %R4, %D2<imp-use,kill>, %D7<imp-use,kill>, %D7<imp-def&g...

...gt; %D7<imp-def> > replaced by: %R15<def> = TFR %R4, %D7<imp-def> > > The R4 is a subreg of D2 double register (basically R0:R1==D0; R4:R5==D2 > etc.). After this copy D2 is dead, and is marked as such. > Register allocator did not mark R4 as <kill>, and when ExpandPostRA copies > operands, it loses the live range marker. > > My questions - is this a known issue? ...and should R4 has been marked as > <kill> in the original instruction? It's not a bug as such. It is OK for kill flags to be missing. It's weird that R4 isn't killed out...

On Fri, 11 May 2012 10:26:41 -0500 <dag at cray.com> wrote: > Hal Finkel <hfinkel at anl.gov> writes: > > >> Actually, we don't have any problem releasing tests. We have done > >> so before when sending patches. The problem is the people we got > >> the tests from. Some are from proprietary test suites, others are > >> from sensitive

Hi, All, I want to add one intrinsic function for my particular backend. Let's say the intrinsic function is named "foo" which takes two i32 inputs and has one i32 output. First, I add this line "def int_foo : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadArgMem]>;" in /include/llvm/IR/Intrinsics.td. Then, in my target/InstrInfo.td, I'm supposed

Hal Finkel <hfinkel at anl.gov> writes: >> Actually, we don't have any problem releasing tests. We have done so >> before when sending patches. The problem is the people we got the >> tests from. Some are from proprietary test suites, others are from >> sensitive codes, etc. It's often not up to us at all. > > I completely understand. Why don't

...no optimization has already taken place. > Thus, the added machine code will be optimized in the same way than any > other options of the program. Moreover, you still have the virtual register > abstraction allowing you to be more flexibility in your implementation. > > You also have ExpandPostRA pass. This one commes right after register > allocation and the addition of the prolog-epilog. It calls > TargetInstrInfo::expandPostRAPseudo() giving a chance to the target to > extend the pseudo-instruction encountered. For the backend X86, the > TargetInstrInfo concrete implementatio...