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2014 Aug 08
6
[LLVMdev] Plan to optimize atomics in LLVM
...ple on Power a > seq_cst store has a fence before it, while on ARM it has a fence > both before and after it (per http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html) That certainly seems to suggest some kind of parametrisation. > For this exact reason, I am planning on splitting AtomicExpandLoadLinkedPass > in a target-independent and a target-dependent file: the current pass claims > to be target-independent but is actually designed for ARM: for example it > puts a release-fence before a seq_cst CAS, which would be unsound on Power > if the backend was more agressive and using lws...