Displaying 2 results from an estimated 2 matches for "expandaddsub".
2008 Sep 08
0
[LLVMdev] adde/addc
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I needed to do exactly the same for my target. I set ISD::ADD to be
custom expanded (setOperationAction(ISD::ADD, MVT::i64, Custom)) and the
same for ISD::SUB. I then added the following code to my target to do
the expansion:
ExpandADDSUB(SDNode *N, SelectionDAG &DAG)
{
assert(N->getValueType(0) == MVT::i64 &&
(N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
"Unknown operand to lower!");
// Extract components
SDOperand LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
N->getO...
2008 Sep 08
6
[LLVMdev] adde/addc
My target doesn't support 64 bit arithmetic, so I'd like to supply
definitions for adde/addc. The problem is I can't seem to figure out the
magic. Here's an example of what I need to generate:
# two i64s in r5/r6 and r7/r8
# result in r1/r2, carry in r3
# adde
add r2, r6, r8
cmpltu r3, r2, r6 # compute carry
# addc
add r1, r5, r7
add r1, zero, r3
Is this