Displaying 8 results from an estimated 8 matches for "exitregion".
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2012 Jun 06
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...rmail/llvmdev/2005-September/004798.html
In order to build bundles, we have added a new bottom-up MIScheduler,
right after reg coalescing, which behaves much like ScheduleDAGVLIW but
without hazard recognizing. Due to some tricky instructions, we cannot
schedule on the DAG. Bundles are built at exitRegion() in the scheduling
process and the live interval information is updated correctly. After
this, the RA is aware of bundles, at least from a LiveInterval point of
view, and I had some problems regarding the rematerialization.
AFAIK, the RA cannot remat if the target instruction is not the bundle...
2012 Jun 06
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...puting interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we cannot
> schedule on the DAG. Bundles are built at exitRegion() in the scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles, at least from a LiveInterval point of
> view, and I had some problems regarding the rematerialization.
>
> AFAIK, the RA cannot remat if the target inst...
2012 Mar 29
0
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...for two approaches to bundling:
1) Bundler operates on a larger scope than the scheduler (preferred): isSchedulingBoundary is true for branches, calls, and other strange barriers. Instructions can be reordered between the boundaries during schedule(), and the bundler can operate across regions via exitRegion() and finishBlock(). You will still have DAG edges from the instruction that a branch depends on to the branch (captured by ExitSU), but you won't have any DAG edges crossing the boundary.
2) Scheduler and bundler operate on the same scope (an entire block): isSchedulingBoundary = false and al...
2012 Mar 29
2
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
On Thu, Mar 29, 2012 at 02:57:27PM -0500, Sergei Larin wrote:
> Tom,
>
> I do not have your call stack, but packetizer calls
> ScheduleDAGInstrs::buildSchedGraph to create dependency model. If this is
> the first time you use the new MI sched infrastructure (like your target has
> not implemented misched yet) there might be some work needed to implement
> couple target
2012 Jun 07
2
[LLVMdev] Instruction bundles before RA: Rematerialization
...> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like
ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we
cannot
> schedule on the DAG. Bundles are built at exitRegion() in the
scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles, at least from a LiveInterval
point of
> view, and I had some problems regarding the rematerialization.
>
> AFAIK, the RA ca...
2012 Mar 30
1
[LLVMdev] VLIWPacketizerList: failing to schedule terminators
...proaches to bundling:
>
> 1) Bundler operates on a larger scope than the scheduler (preferred): isSchedulingBoundary is true for branches, calls, and other strange barriers. Instructions can be reordered between the boundaries during schedule(), and the bundler can operate across regions via exitRegion() and finishBlock(). You will still have DAG edges from the instruction that a branch depends on to the branch (captured by ExitSU), but you won't have any DAG edges crossing the boundary.
>
> 2) Scheduler and bundler operate on the same scope (an entire block): isSchedulingBoundary = fa...
2012 Jun 07
0
[LLVMdev] Instruction bundles before RA: Rematerialization
...omputing interference.
> In order to build bundles, we have added a new bottom-up MIScheduler,
> right after reg coalescing, which behaves much like ScheduleDAGVLIW but
> without hazard recognizing. Due to some tricky instructions, we cannot
> schedule on the DAG. Bundles are built at exitRegion() in the scheduling
> process and the live interval information is updated correctly. After
> this, the RA is aware of bundles, at least from a LiveInterval point of
> view, and I had some problems regarding the rematerialization.
>
> AFAIK, the RA cannot remat if the target instruct...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...nits.
>> - SUnits = SchedulerImpl->SUnits;
>> + assert(VLIWScheduler&& "VLIW Scheduler is not initialized!");
>> + VLIWScheduler->enterRegion(MBB, BeginItr, EndItr, MBB->size());
>> + VLIWScheduler->schedule();
>> + VLIWScheduler->exitRegion();
>> +
>> + // Generate MI -> SU map.
>> + //std::map<MachineInstr*, SUnit*> MIToSUnit;
>> + MIToSUnit.clear();
>> + for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) {
>> + SUnit *SU =&VLIWScheduler->SUnits[i];
>...